Lithography simulation is an essential technique for today's semiconductor manufacturing process. Although several rigorous models have been proposed, these methods are time-consuming. In order to calculate a full chip in realistic time, a fast and accurate resist model is essential. This paper proposes a new compact resist model using an arbitrary convolution kernel. The convolution formula can be described as a system of linear equations, therefore, we can determine the convolution kernel by solving the system of linear equations. However, it is hard to find the effective solution, because it is an ill-posed linear inverse problem due to the measurement constraints. Therefore, the key point of our method is how to solve the ill-posed linear inverse problem. In this paper, we explain the details and effectiveness of our method.
Lithography hotspot detection using lithography simulation (LCC) in a design stage is one of important techniques in order to avoid yield loss caused by the hotspots. Conventional LCC should detect all hotspots observed on wafer and reduce false errors which are not hotspots on wafer. However, the conventional LCC is not enough to meet the requirement. In this paper, we propose a multi-criteria hotspot detection method with a pattern classification technique. The proposed method uses a peak intensity value as the criterion and different criteria are used for different pattern categories. The categories are created based on K-means algorithm. Experimental results show our proposed method can reduce a number of false errors by 75% without any overlooking of hotspots.
Lithography hotspot detection and correction in the layout design phase is important to suppress manufacturing yield loss. Although machine learning based hotspot detection methods are considered as effective solutions over conventional lithography simulation, it is still difficult to apply them to practical layout design tasks because of a trade-off between detection accuracy and false alarms. In this paper, we propose a fast, accurate and reliable method to detect lithography hotspot candidates based on coherence map. Experimental results show that our method outperforms typical machine learning based hotspot detection models on industrial benchmark.
Machine learning is a powerful tool to learn a predictive model which can give a statistical or probabilistic solution to a problem. It has widely been applied to major issues in design for manufacturing field, such as SRAF generation, compact resist model and lithography hotspot detection. Although it is sometimes considered as an effective technique that solves serious problems, a reliable solution is rarely achieved without detailed understanding of the problem and appropriate problem formulation. In this paper, we will discuss basic concept and recent results of machine learning applications in design for manufacturing.
Lithography simulation is an essential technique for today’s semiconductor manufacturing process. In order to calculate an entire chip in realistic time, compact resist model is commonly used. The model is established for faster calculation. To have accurate compact resist model, it is necessary to fix a complicated non-linear model function. However, it is difficult to decide an appropriate function manually because there are many options. This paper proposes a new compact resist model using CNN (Convolutional Neural Networks) which is one of deep learning techniques. CNN model makes it possible to determine an appropriate model function and achieve accurate simulation. Experimental results show CNN model can reduce CD prediction errors by 70% compared with the conventional model.
As technology node shrinks down, hotspots, i.e. patterning failures on wafer after etching process, become an inevitable
problem. The main cause of such hotspots is low contrast of aerial image. There are several methods that can improve
aerial image contrast such as SRAF insertion and OPC. However, it is difficult to fix all hotspots by applying only SRAF
and OPC in advanced technology node. This paper proposes a new post-layout optimization method, before SRAF and
OPC, based on SOCS kernel for improving aerial image contrast and reducing hotspots. Experimental results show average
4nm PV-band improvement, as a result of contrast improvement.
Lithography simulation is an essential technique for today's semiconductor manufacturing process. In order to calculate an entire chip in realistic time, compact resist model is commonly used. The model is established for faster calculation. To have accurate compact resist model, it is necessary to fix a complicated non-linear model function. However, it is difficult to decide an appropriate function manually because there are many options. This paper proposes a new compact resist model using CNN (Convolutional Neural Networks) which is one of deep learning techniques. CNN model makes it possible to determine an appropriate model function and achieve accurate simulation. Experimental results show CNN model can reduce CD prediction errors by 70% compared with the conventional model.
Effective layout pattern sampling is a fundamental component for lithography process optimization, hotspot detection, and model calibration. Existing pattern sampling algorithms rely on either vector quantization or heuristic approaches. However, it is difficult to manage these methods due to the heavy demands of prior knowledge, such as high-dimensional layout features and manually tuned hypothetical model parameters. We present a self-contained layout pattern sampling framework, where no manual parameter tuning is needed. To handle high dimensionality and diverse layout feature types, we propose a nonlinear dimensionality reduction technique with kernel parameter optimization. Furthermore, we develop a Bayesian model-based clustering, through which automatic sampling is realized without arbitrary setting of model parameters. The effectiveness of our framework is verified through a sampling benchmark suite and two applications: lithography hotspot detection and optical proximity correction.
KEYWORDS: Lithography, Computer simulations, 193nm lithography, Feature extraction, Simulation of CCA and DLA aggregates, Semiconducting wafers, Manufacturing, Etching, Scanning electron microscopy, Photomasks
As minimum feature sizes shrink, unexpected hotspots appear on wafers. Therefore, it is important to detect and fix these hotspots at design stage to reduce development time and manufacturing cost. Currently, as the most accurate approach, lithography simulation is widely used to detect such hotspots. However, it is known to be time-consuming. This paper proposes a novel aerial image synthesizing method using regression and minimum lithography simulation for only hotspot detection. Experimental results show hotspot detection on the proposed method is equivalent compared with the results on the conventional hotspot detection method which uses only lithography simulation with much less computational cost.
Lithography hotspot detection in the physical verification phase is one of the most important techniques in today's optical lithography based manufacturing process. Although lithography simulation based hotspot detection is widely used, it is also known to be time-consuming. To detect hotspots in a short runtime, several machine learning based methods have been proposed. However, it is difficult to realize highly accurate detection without an increase in false alarms because an appropriate layout feature is undefined. This paper proposes a new method to automatically extract a proper layout feature from a given layout for improvement in detection performance of machine learning based methods. Experimental results show that using a deep neural network can achieve better performance than other frameworks using manually selected layout features and detection algorithms, such as conventional logistic regression or artificial neural network.
KEYWORDS: Optical proximity correction, Data modeling, Model-based design, Performance modeling, Statistical modeling, Simulation of CCA and DLA aggregates, Lithography, Feature extraction, Monte Carlo methods, Optics manufacturing
Optical proximity correction (OPC) is one of the most important techniques in today’s optical lithography-based manufacturing process. Although the most widely used model-based OPC is expected to achieve highly accurate correction, it is also known to be extremely time-consuming. This paper proposes a regression model for OPC using a hierarchical Bayes model (HBM). The goal of the regression model is to reduce the number of iterations in model-based OPC. Our approach utilizes a Bayes inference technique to learn the optimal parameters from given data. All parameters are estimated by the Markov Chain Monte Carlo method. Experimental results show that utilizing HBM can achieve a better solution than other conventional models, e.g., linear regression-based model, or nonlinear regression-based model. In addition, our regression results can be used as the starting point of conventional model-based OPC, through which we are able to overcome the runtime bottleneck.
Under the low-k1 lithography process, lithography hotspot detection and elimination in the physical verification phase have become much more important for reducing the process optimization cost and improving manufacturing yield. This paper proposes a highly accurate and low-false-alarm hotspot detection framework. To define an appropriate and simplified layout feature for classification model training, we propose a novel feature space evaluation index. Furthermore, by applying a robust classifier based on the probability distribution function of layout features, our framework can achieve very high accuracy and almost zero false alarm. The experimental results demonstrate the effectiveness of the proposed method in that our detector outperforms other works in the 2012 ICCAD contest in terms of both accuracy and false alarm.
KEYWORDS: Optical proximity correction, Data modeling, Model-based design, Statistical modeling, Performance modeling, Feature extraction, Simulation of CCA and DLA aggregates, Lithography, Monte Carlo methods, Statistical analysis
Optical Proximity Correction (OPC) is one of the most important techniques in today's optical lithography based manufacturing process. Although the most widely used model-based OPC is expected to achieve highly accurate correction, it is also known to be extremely time-consuming. This paper proposes a regression model for OPC using a Hierarchical Bayes Model (HBM). The goal of the regression model is to reduce the number of iterations in model-based OPC. Our approach utilizes a Bayes inference technique to learn the optimal parameters from given data. All parameters are estimated by the Markov Chain Monte Carlo method. Experimental results show that utilizing HBM can achieve a better solution than other conventional models, e.g., linear regression based model, or non-linear regression based model. In addition, our regression results can be fed as the starting point of conventional model based OPC, through which we are able to overcome the runtime bottleneck.
Although a number of factors relating to lithography and material stacking have been investigated to realize hotspot-free wafer images, hotspots are often still found on wafers. For the 22-nm technology node and beyond, the detection and repair of hotspots with lithography simulation models is extremely time-consuming. Thus, hotspots represent a critical problem that not only causes delays to process development but also represents lost business opportunities. In order to solve the time-consumption problem of hotspots, this paper proposes a new method of hotspot prevention and detection using an image recognition technique based on higher-order local autocorrelation, which is adopted to extract geometrical features from a layout pattern. To prevent hotspots, our method can generate proper verification patterns to cover the pattern variations within a chip layout to optimize the lithography conditions. Moreover, our method can realize fast hotspot detection without lithography simulation models. Obtained experimental results for hotspot prevention indicated excellent performance in terms of the similarity between generated proposed patterns and the original chip layout patterns, both geometrically and optically. Moreover, the proposed hotspot detection method could achieve turn-around time reductions of >95% for just one CPU, compared to the conventional simulation-based approach, without accuracy losses.
KEYWORDS: Lithography, Data storage, Optical proximity correction, Microelectronics, Design for manufacturability, Current controlled current source, Intellectual property, Time metrology
Layout verification is essential in the cutting-edge generation. Generally, it uses a lithography simulation (Lithography
Compliance Check: LCC) and requires a lot of calculation time. In order to reduce LCC time, we propose a clean pattern
matching method by means of a "clean pattern library". The proposed method searches for patterns without hotspots
(clean patterns) which usually occupy the most of the chip area. The conventional hotspot pattern matching method has
no guarantee that unmatched area is hotspot-free, so LCC is usually applied to the unmatched area. On the other hand,
the proposed matching method searches for "clean" patterns so that most of the area need not to be verified. As a result,
LCC time can be reduced. This paper shows the detailed flow of the proposed matching method. We present the
experimental results of layout verification in our 40nm system LSI designs and the effectiveness of the proposed method
is confirmed.
Although lithography conditions, such as NA, illumination condition, resolution enhancement technique (RET), and
material stack on wafer, have been determined to obtain hotspot-free wafer images, hotspots are still often found on
wafers. This is because the lithography conditions are optimized with a limited variety of patterns. For 40 nm technology
node and beyond, it becomes a critical issue causing not only the delay of process development but also the opportunity
loss of the business. One of the easiest ways to avoid unpredictable hotspots is to verify an enormous variety of patterns
in advance. This, however, is time consuming and cost inefficient.
This paper proposes a new method to create a group of patterns to cover pattern variations in a chip layout based on
Higher-Order Local Autocorrelation (HLAC), which consists of two phases. The first one is the "analyzing phase" and
the second is the "generating phase". In the analyzing phase, geometrical features are extracted from actual layouts using
the HLAC technique. Those extracted features are statistically analyzed and define the "feature space". In the generating
phase, a group of patterns representing actual layout features are generated by correlating the feature space and the
process margin. By verifying the proposed generated patterns, the lithography conditions can be optimized efficiently
and the number of hotspots dramatically reduced.
Below 40nm design node, systematic variation due to lithography must be taken into consideration during
the early stage of design.
So far, litho-aware design using lithography simulation models has been widely applied to assure that
designs are printed on silicon without any error.
However, the lithography simulation approach is very time consuming, and under time-to-market pressure,
repetitive redesign by this approach may result in the missing of the market window.
This paper proposes a fast hotspot detection support method by flexible and intelligent vision system image
pattern recognition based on Higher-Order Local Autocorrelation.
Our method learns the geometrical properties of the given design data without any defects as normal
patterns, and automatically detects the design patterns with hotspots from the test data as abnormal patterns.
The Higher-Order Local Autocorrelation method can extract features from the graphic image of design
pattern, and computational cost of the extraction is constant regardless of the number of design pattern
polygons.
This approach can reduce turnaround time (TAT) dramatically only on 1CPU, compared with the
conventional simulation-based approach, and by distributed processing, this has proven to deliver linear
scalability with each additional CPU.
SRAF (Sub Resolution Assist Feature) technique has been widely used for DOF enhancement. Below 40nm design
node, even in the case of using the SRAF technique, the resolution limit is approached due to the use of hyper NA
imaging or low k1 lithography conditions especially for the contact layer. As a result, complex layout patterns or random
patterns like logic data or intermediate pitch patterns become increasingly sensitive to photo-resist pattern fidelity. This
means that the need for more accurate resolution technique is increasing in order to cope with lithographic patterning
fidelity issues in low k1 lithography conditions. To face with these issues, new SRAF technique like model based SRAF
using an interference map or inverse lithography technique has been proposed. But these approaches don't have enough
assurance for accuracy or performance, because the ideal mask generated by these techniques is lost when switching to a
manufacturable mask with Manhattan structures. As a result it might be very hard to put these things into practice and
production flow.
In this paper, we propose the novel method for extremely accurate SRAF placement using an adaptive search algorithm.
In this method, the initial position of SRAF is generated by the traditional SRAF placement such as rule based SRAF,
and it is adjusted by adaptive algorithm using the evaluation of lithography simulation. This method has three advantages
which are preciseness, efficiency and industrial applicability. That is, firstly, the lithography simulation uses actual
computational model considering process window, thus our proposed method can precisely adjust the SRAF positions,
and consequently we can acquire the best SRAF positions. Secondly, because our adaptive algorithm is based on optimal
gradient method, which is very simple algorithm and rectilinear search, the SRAF positions can be adjusted with high
efficiency. Thirdly, our proposed method, which utilizes the traditional SRAF placement, is easy to be utilized in the
established workflow. These advantages make it possible to give the traditional SRAF placement a new breath of life for
low k1.
This paper proposes an approach to improving pattern extraction efficiency for character projection lithography
(CPL). CPL is a promising technology for electron beam direct-write lithography. The advantage of CPL is
the reduced number of electron beam (EB) shots compared to conventional variably-shaped beam lithography,
because character patterns that frequently appear within a layout can be simultaneously written by a single EB
shot with a CP aperture mask. This means that it is important to extract frequently-used character patterns
and prepare CP aperture masks in order to reduce the number of EB shots. However, with random logic devices,
each character pattern is subject to being deformed into many different patterns that have complicated optical
proximity correction (OPC) features, which cannot be extracted as a unique CP aperture mask. In order to
overcome this problem, we propose a method of improving the efficiency of pattern extraction for CPL with
random logic devices by employing OPC optimization. Our proposed method can reduce the variety in the
deformed patterns with two developed cell-based algorithms: (1) a cell grouping algorithm that categorizes
differentiated cells and extracts some typical cell groups, and (2) an OPC optimization algorithm that regards
the cells in a group as one typical cell and corrects for the OPC features of a typical cell to form a CP aperture
mask. In conducted experiments, we successfully achieved a 30% improvement in extraction efficiency.
This paper proposes a new approach to optical proximity correction (OPC) using an adjustable OPCed cell and genetic algorithms (GA) to achieve optimal OPC feature generation for the full-chip area at fast operational speeds. GA is an efficient optimization technique based on population genetics. In this new approach, an adjustable OPCed cell consists of two parts. The first part is the original design data. The second part consists of two kinds of OPC features. The first kind is referred to as "fixed features", which include OPC feature data from a conventional OPC technique. The second kind, named "adjustable features", are located in the peripheral regions of the cell and include adjustable OPC variables. As the values of these variables are greatly influenced by neighboring cell patterns, the variables are quickly optimized by the GA after chip layout. The effectiveness of this approach, in terms of reduced times for accurate simulations and repeated modification of OPCed features, is demonstrated through computational experiments.
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