During the past years, the processor-memory performance gap, also known as “Memory Wall” problem, has forced designers to allocate more than 50% of the chip real-estate for caching purposes to alleviate limited memory bandwidth. Optical technology holds the credentials of delivering high-bandwidth and energy-efficient photonic integrated memories that could revisit the traditional computing architectures. The migration, however, to fully functional and practical optical RAMs will require the exploitation of wavelength dimension as well as seamless cooperation between storage and peripheral decoding units, for efficient RAM architectural layouts. In this paper we present the first demonstration of an all-optical 8-bit RAM storage unit comprising WDM-enabled 2×4 Row and 1×4 Column Decoders and a 2×4-bit optical RAM Bank for storing a 20Gb/s 4-bit WDM-formatted optical data word per row. The proposed scheme incorporates a shared multi-λ SOA-MZI Access Gate (AG) per Word Line (WL) for granting access-control to the appropriate word line, WL “00” or WL “01”, and a passive Column Decoder that directs the incoming WDM-formatted data words to the respective RAM cells. Each RAM cell is in turn based on an elementary monolithically integrated InP photonic Flip-Flop (FF). The proposed architecture is experimentally verified for successful Write operation of a 4-bit WDM word to a selected 4-bit RAM row at 20Gb/s RAM throughput and a peak power penalty within the range of [7.8-10.7] dB, promising a 4× speed-up in memory-access throughput and paving the way for high-bandwidth multi-bit optical RAM-architectures that may relax the memory-bottleneck of computing architectures.
Optical Random Access Memories (RAMs) have been conceived as high-bandwidth alternatives of their electronic counterparts, raising expectations for ultra-fast operation that can resolve the ns-long electronic RAM access bottleneck. In addition, with electronic Address Look-Up tables operating still at speeds of only up to 1 GHz, the constant increase in optical switch i/o data rates will yield severe latency and energy overhead during forwarding operations. In this invited paper, we present an overview of our recent research, introducing an all-optical RAM cell that performs both Write and Read functionalities at 10Gb/s, reporting on a 100% speed increase compared to state-of-the-art optical/electrical RAM demonstrations. Moreover, we present an all-optical Ternary-CAM cell that operates again at 10 Gb/s, doubling the speed of the fastest optical/electrical CAMs so far. To achieve this, we utilized a monolithically integrated InP optical Flip-Flop and a Semiconductor Optical Amplifier-Mach-Zehnder Interferometer (SOA-MZI) operating as an Access Gate to the RAM, and as an XOR gate to the T-CAM. These two demonstrations pave the way towards the vision of integrated photonic look-up memory architectures in order to relieve the memory bottlenecks.
The ever-increasing energy consumption of Data Centers (DC), along with the significant waste of resources that is observed in traditional DCs, have forced DC operators to invest in solutions that will considerably improve energy efficiency. In this context, Rack- and board-scale resource disaggregation is under heavy research, as a groundbreaking innovation that could amortize the energy and cost impact caused by the vast diversity in resource demand of emerging DC workloads. However disaggregation, by breaking apart the critical CPU-to-memory path, introduces a challenging set of requirements in the underlying network infrastructure, that has to support low-latency and high-throughput communication for a high number of nodes.
In this paper we present our recent work on optical interconnects towards enabling resource disaggregation both on Rack-level as well as on board-level. To this end, we have demonstrated the Hipoλaos architecture that can efficiently integrate Spanke-based switching with AWGR-based wavelength routing and optical feedforward buffering into highport switch layouts. The proof-of-concept Hipoλaos prototype, based on the 1024-port layout, provide latency performance of 456ns, while system level evaluations reveal sub-μs latency performance for a variety of synthetic traffic profiles. Moving towards high-capacity board-level interconnects, we present the latest achievements realized within the context of H2020-STREAMS project, where single-mode optical PCBs hosting Si-based routing modules and mid-board optics are exploited towards a massive any-to-any, buffer-less, collision-less and extremely low latency routing platform with 25.6Tb/s throughput. Finally, we combine the Hipolaos and STREAMS architectures in a dual-layer switching scheme and evaluate its performance via system-level simulations.
The rapid increase of bandwidth requirements across the entire hierarchy of Data Center (DC) networks, ranging from chip-to-chip, board-to-board up to rack-to-rack communications, puts strenuous requirements in the underlying network infrastructure that has to offer high-bandwidth and low-latency interconnection under a low-energy and low-cost envelope. Arrayed Waveguide Grating Router (AWGR)-based optical interconnections have emerged as a powerful architectural framework that can overcome the currently deployed electrical interconnect bottlenecks leveraging the wavelength division multiplexing (WDM) and the cyclic routing properties of AWGRs to offer one-hop, all-to-all communication when employed as N×N routers. However, the majority of previous silicon (Si)-based integrated AWGR demonstrations has either targeted C-band operation, despite the dominance of the O-band spectral region in the DC interconnection domain, or offered coarse-WDM (CWDM) functionality and, as such, were limited in terms of AWGR port count. In this article, we present for the first time to our knowledge, a Dense-WDM (DWDM) 16×16 Si-photonic cyclic-frequency AWGR device targeting O-band routing applications. The fabricated AWGR device features a channel spacing of 1.063 nm (189 GHz), a free spectral range of 17.8 nm (3.15 THz) and a 3-dB bandwidth of 0.655 nm (116 GHz). Its proper cyclic frequency operation was experimentally verified for all 16 channels with channel peak insertion loss values in the range of 3.9 dB to 8.37 dB, yielding a channel loss non-uniformity of 4.47 dB. Its compact footprint of 0.27×0.71 mm2 and low crosstalk of 21.65 dB highlight its potential for employment in future AWGR-based interconnection schemes.
The ever-increasing demands in traffic fueled by bandwidth hungry applications are pushing data centers to their limits challenging the capacity and scalability of currently established transceiver and switching technologies in data center interconnection (DCI) networks. Coherent optics emerged as a promising solution for inter-DCIs offering unprecedented capacities closer to data centers and relaxing the power budget restrictions of the link. QAMeleon, an EU funded R and D project, is developing a new generation of faster and greener sliceable bandwidth-variable electro-optical transceivers and WSS switches able to handle up to 128 Gbaud optical signals carrying flexible M-QAM constellations and novel modulation techniques. A summary of the progress on the QAMeleon transponder and Reconfigurable Optical Add/Drop Multiplexer (ROADM) concepts is presented in this paper.
As data centers constantly expand, electronic switches are facing the challenge of enhanced scalability and the request for increased pin-count and bandwidth. Photonic technology and wavelength division multiplexing have always been a strong alternative for efficient routing and their potential was already proven in the telecoms. CWDM transceivers have emerged in the board-to-board level interconnection, revealing the potential for wavelength-routing to be applied in the datacom and an AWGR-based approach has recently been proposed towards building an optical multi-socket interconnection to offer any-to-any connectivity with high aggregated throughput and reduced power consumption.
Echelle gratings have long been recognized as the multiplexing block exhibiting smallest footprint and robustness in a wide number of applications compared to other alternatives such as the Arrayed Waveguide Grating. Such filtering devices can also perform in a similar way to cyclical AWGR and serve as mid-board routing platforms in multi-socket environments. In this communication, we present such a 3x3 Echelle grating integrated on thick SOI platform with aluminum-coated facets that is shown to perform successful wavelength-routing functionality at 10 Gb/s. The device exhibits a footprint of 60x270 μm2, while the static characterization showed a 3 dB on–chip loss for the best channel. The 3 dB-bandwidth of the channels was 4.5 nm and the free spectral range was 90 nm. The echelle was evaluated in a 2x2 wavelength routing topology, exhibiting a power penalty of below 0.4 dB at 10-9 BER for the C-band. Further experimental evaluations of the platform involve commercially available CWDM datacenter transceivers, towards emulating an optically-interconnected multi-socket environment traffic scenario.
The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.
Hybrid integration on Silicon-on-Insulator (SOI) has emerged as a practical solution for compact and high-performance
Photonic Integrated Circuits (PICs). It aims at combining the cost-effectiveness and CMOS-compatibility benefits of the
low-loss SOI waveguide platform with the versatile active optical functions that can be realized by III-V photonic
materials. The utilization of SOI, as an integration board, with μm-scale dimensions allows for an excellent optical mode
matching between silicon rib waveguides and active chips, allowing for minimal-loss coupling of the pre-fabricated IIIV
components. While dual-facet coupling as well as III-V multi-element array bonding should be employed to enable
enhanced active on-chip functions, so far only single side SOA bonding has been reported. In the present
communication, we present a novel integration scheme that flip-chip bonds a 6-SOA array on 4-μm thick SOI
technology by coupling both lateral SOA facets to the waveguides, and report on the experimental results of wavelength
conversion operation of a dual-element Semiconductor Optical Amplifier – Mach Zehnder Interferometer (SOA-MZI)
circuit. Thermocompression bonding was applied to integrate the pre-fabricated SOAs on SOI, with vertical and
horizontal alignment performed successfully at both SOA facets. The demonstrated device has a footprint of 8.2mm x
0.3mm and experimental evaluation revealed a 12Gb/s wavelength conversion operation capability with only 0.8dB
power penalty for the first SOA-MZI-on-SOI circuit and a 10Gb/s wavelength conversion operation capability with 2 dB
power penalty for the second SOA-MZI circuit. Our experiments show how dual facet integration can significantly
increase the level of optical functionalities achievable by flip-chip hybrid technology and pave the way for more
advanced and more densely PICs.
Towards achieving a functional RAM organization that reaps the advantages offered by optical technology, a complete set of optical peripheral modules, namely the Row (RD) and Column Decoder (CD) units, is required. In this perspective, we demonstrate an all-passive 2×4 optical RAM RD with row access operation and subsequent all-passive column decoding to control the access of WDM-formatted words in optical RAM rows. The 2×4 RD exploits a WDM-formatted 2-bit-long memory WordLine address along with its complementary value, all of them encoded on four different wavelengths and broadcasted to all RAM rows. The RD relies on an all-passive wavelength-selective filtering matrix (λ-matrix) that ensures a logical ‘0’ output only at the selected RAM row. Subsequently, the RD output of each row drives the respective SOA-MZI-based Row Access Gate (AG) to grant/block the entry of the incoming data words to the whole memory row. In case of a selected row, the data word exits the row AG and enters the respective CD that relies on an allpassive wavelength-selective Arrayed Waveguide Grating (AWG) for decoding the word bits into their individual columns. Both RD and CD procedures are carried out without requiring any active devices, assuming that the memory address and data word bits as well as their inverted values will be available in their optical form by the CPU interface. Proof-of-concept experimental verification exploiting cascaded pairs of AWGs as the λ-matrix is demonstrated at 10Gb/s, providing error-free operation with a peak power penalty lower than 0.2dB for all optical word channels.
Optical RAM has emerged as a promising solution for overcoming the “Memory Wall” of electronics, indicating the use of light in RAM architectures as the approach towards enabling ps-regime memory access times. Taking a step further towards exploiting the unique wavelength properties of optical signals, we reveal new architectural perspectives in optical RAM structures by introducing WDM principles in the storage area. To this end, we demonstrate a novel SOAbased multi-wavelength Access Gate for utilization in a 4x4 WDM optical RAM bank architecture. The proposed multiwavelength Access Gate can simultaneously control random access to a 4-bit optical word, exploiting Cross-Gain-Modulation (XGM) to process 8 Bit and Bit channels encoded in 8 different wavelengths. It also suggests simpler optical RAM row architectures, allowing for the effective sharing of one multi-wavelength Access Gate for each row, substituting the eight AGs in the case of conventional optical RAM architectures. The scheme is shown to support 10Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15mW/Gbit/s. All 8 wavelength channels demonstrate error-free operation with a power penalty lower than 3 dB for all channels, compared to Back-to-Back measurements. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption. Moreover, exploitation of the wavelength entity can release significant potential towards reconfigurable optical cache mapping schemes when using the wavelength dimension for memory addressing.
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