Mr. Tim Chen Profile

Tim Chen

Product & Applications Manager

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Publications (11)

Proceedings Article | 20 May 2006 Paper

A single-exposure approach for patterning 45nm flash/DRAM contact hole mask

Ting Chen, Doug Van Den Broeke, Edita Tejnil, Stephen Hsu, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep De Vocht, Noel Corcoran, J. Fung Chen, Eddy van der Heijden, Jo Finders, Andre Engelen, Robert Socha

Proceedings Volume 6283, 62831A (2006) https://doi.org/10.1117/12.681873

KEYWORDS: Optical proximity correction, Electroluminescence, Optical lithography, Printing, Photomasks, Lithographic illumination, Semiconducting wafers, Diffractive optical elements, Manufacturing, Nanoimprint lithography

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Contact hole (CH) patterning for DRAM/Flash presents a key challenge for design rule below 50nm due to aggressive low-k₁ conditions common in the leading DRAM/Flash memory designs. Combining optical proximity corrections (OPC) to the mask and optimized illumination has become an important part of production-worthy lithography processes for the 65nm node. At k₁<0.31, both resolution and imaging contrast can become severely limited at NA<0.85 with some commonly available off-axis illumination sources. Hyper-NA and immersion lithography with polarized illumination capability can significantly increase the process latitude and is indispensable for manufacturing at sub-50nm design rule and beyond. In this work, we describe our single-exposure approach for patterning Flash/DRAM contact-hole patterns with 120nm minimum pitch (and 60nm CH target CD). We use 6% attPSM dark-field mask both in simulations and for wafer exposures on ASML XT:1700i at NA=1.2. We begin with illumination source optimization using full vector high-NA simulation with (unpolarized and Y polarized illumination) a production resist stack and taking into account during the optimization all manufacturability requirements for the corresponding diffractive optical element (DOE) that produces the optimized source at the mask level. Using the optimized source, model-based OPC treatment was performed, which includes scattering bars (SB) placement using IML^TM technology and model-based CH feature biasing (MOPC) to achieve the optimum pattern printing fidelity in-focus and process latitude. To further increase of the depth of focus (DOF) for common process window (CPW) from 150nm to >250m, we used the focus scan (or, focus drilling) technique which is available in today's leading 193nm scanners. Our results showed that, for the 120nm minimum pitch Flash CH patterns used, hyper-NA (NA>1) and immersion lithography (ASML XT:1700i platform was used in both simulation and scheduled for wafer exposures) is necessary, together with optimized illumination and model based OPC treatment, to achieve a yielding baseline process (common process window with DOF ~100nm). We also demonstrate that polarized illumination can significantly enhance the overall imaging performance, i.e., worst-case DOF can be increased >25% with optimized source, which is limited by the dense pitch CH arrays for this particular Flash CH pattern. With focus scan enabled for imaging, we show that the worst-case individual DOF can be easily doubled (from 150nm to >300nm) and EL at best focus (BF) remains >10% even at the largest focus range settings (400nm). The common process window decreased as focus scan range was increased, indicating that to maintain optimum common process window, MOPC treatment must be also performed under the same focus scan conditions. Patterning optimization (from illumination optimization to OPC) with focus scan enabled shows excellent promise as a single-exposure solution for patterning this 45nm Flash CH pattern and beyond.

Proceedings Article | 15 March 2006 Paper

Patterning 45nm flash/DRAM contact hole mask with hyper-NA immersion lithography and optimized illumination

Ting Chen, Doug Van Den Broeke, Stephen Hsu, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep de Vocht, Noel Corcoran, Fung Chen, Eddy van der Heijden, Jo Finders, Andre Engelen, Robert Socha

Proceedings Volume 6154, 61541O (2006) https://doi.org/10.1117/12.656982

KEYWORDS: Electroluminescence, Semiconducting wafers, Photomasks, Diffractive optical elements, Optical lithography, Printing, Nanoimprint lithography, Optical proximity correction, Polarization, Finite element methods

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Patterning contact-hole mask for Flash/DRAM is probably one of the most challenging tasks for design rule below 50nm due to the extreme low-k₁ printing conditions common in the memory designs. When combined with optical proximity corrections (OPC) to the mask, using optimized illumination has become a viable part of the production lithography process for 65nm node. At k₁<0.31, both resolution and imaging contrast can become severely limited by some of the current imaging tools with NA<0.85 and using standard illumination sources. Hyper-NA immersion lithography increases the process latitude and is therefore expected to become more indispensable for manufacturing under extreme low-k₁ conditions for sub-50nm design rule. In this work, we describe our process optimization approach for patterning Flash/DRAM contact-hole patterns with 130nm, 120nm, and smaller minimum pitch design rules. Here we use 6% attPSM mask for simulation and actual exposure in ASML XT 1400i (NA=0.93) and 1700i (NA=1.2) respectively. We begin with the illumination source optimization using full vector high-NA calculation (VHNA) with production resist stack and all manufacturability requirements for the source shaping diffractive optical element (DOE) are accounted for during the source optimization. Using the optimized source, IML^TM technology based scattering bars (SB) placement together with model based OPC (MOPC) are applied to the original contact-hole design. In-focus printing and process latitude simulations are used to gauge the performance and manufacturability of the final optimized process, which includes the optimized mask, optimized source and required imaging settings. Our results show that for the 130nm pitch Flash contact-hole patterns, on ASML XT 1400i at NA=0.93, both optimized illumination source and immersion lithography are necessary in order to achieve manufacturability. The worst-case depth of focus (DOF) before SB and MOPC is 100-130nm at 6% EL, without common process window (PW) and with MOPC, the worst-case DOF is >200nm at 6% EL. The latter is in excellent agreement with the wafer results from ASML XT 1400i, and the predicated CDs match well with the measured at isolated, medium and dense pitch contact-holes to within 5nm. For the 120nm pitch Flash contact patterns, ASML XT 1700i at NA=1.2 must be used, together with optimized illumination source, to achieve the same or better process latitude (worst-case DOF at 6% EL), and for the Flash pattern used, further enhancements of >20% in DOF @ 6% EL using Y linear polarization can be achieved, before SB and MOPC. With preliminary SB and MOPC, the worst-case DOF @ 6% EL is increased from 100nm to 150nm and with common PW for all critical CDs, from isolated to dense contact-holes. Two examples of customized polarizations are considered in the above simulations to demonstrate the effects of polarizations on imaging and process latitude for pattern specific contact-holes. The pros and cons of the current patterning solution are discussed and compared with alternatives.

Proceedings Article | 15 March 2006 Paper

Experimental evaluation of Bulls-Eye illumination for assist-free random contact printing at sub-65nm node

Jo Finders, Andre Engelen, Geert Vandenberghe, Joost Bekaert, Tim Chen

Proceedings Volume 6154, 615412 (2006) https://doi.org/10.1117/12.659420

KEYWORDS: Printing, Lithographic illumination, Nanoimprint lithography, Reticles, Photomasks, Eye, Optical lithography, Semiconducting wafers, Lithography, Electroluminescence

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Proceedings Article | 8 November 2005 Paper

Patterning optimization for 55nm design rule DRAM/flash memory using production-ready customized illuminations

Ting Chen, Doug Van Den Broeke, Stephen Hsu, Michael Hsu, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep de Vocht, Fung Chen, Robert Socha, JungChul Park, Keith Gronlund

Proceedings Volume 5992, 599239 (2005) https://doi.org/10.1117/12.633465

KEYWORDS: Electroluminescence, Printing, Nanoimprint lithography, Lithographic illumination, Cerium, Fiber optic illuminators, Manufacturing, Optical proximity correction, Optical lithography, Photomasks

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Illumination optimization, often combined with optical proximity corrections (OPC) to the mask, is becoming one of the critical components for a production-worthy lithography process for 55nm-node DRAM/Flash memory devices and beyond. At low-k₁, e.g. k₁<0.31, both resolution and imaging contrast can be severely limited by the current imaging tools while using the standard illumination sources. Illumination optimization is a process where the source shape is varied, in both profile and intensity distribution, to achieve enhancement in the final image contrast as compared to using the non-optimized sources. The optimization can be done efficiently for repetitive patterns such as DRAM/Flash memory cores. However, illumination optimization often produces source shapes that are "free-form" like and they can be too complex to be directly applicable for production and lack the necessary radial and annular symmetries desirable for the diffractive optical element (DOE) based illumination systems in today's leading lithography tools. As a result, post-optimization rendering and verification of the optimized source shape are often necessary to meet the production-ready or manufacturability requirements and ensure optimal performance gains. In this work, we describe our approach to the illumination optimization for k₁<0.31 DRAM/Flash memory patterns, using an ASML XT:1400i at NA 0.93, where the all necessary manufacturability requirements are fully accounted for during the optimization. The imaging contrast in the resist is optimized in a reduced solution space constrained by the manufacturability requirements, which include minimum distance between poles, minimum opening pole angles, minimum ring width and minimum source filling factor in the sigma space. For additional performance gains, the intensity within the optimized source can vary in a gray-tone fashion (eight shades used in this work). Although this new optimization approach can sometimes produce closely spaced solutions as gauged by the NILS based metrics, we show that the optimal and production-ready source shape solution can be easily determined by comparing the best solutions to the "free-form" solution and more importantly, by their respective imaging fidelity and process latitude ranking. Imaging fidelity and process latitude simulations are performed to analyze the impact and sensitivity of the manufacturability requirements on pattern specific illumination optimizations using ASML XT:1400i and other latest imaging systems. Mask model based OPC (MOPC) is applied and optimized sequentially to ensure that the CD uniformity requirements are met.

Proceedings Article | 28 June 2005 Paper

RET masks for the final frontier of optical lithography

J. Chen, Douglas van den Broeke, Stephen Hsu, Michael Hsu, Tom Laidig, Xuelong Shi, Ting Chen, Robert Socha, Uwe Hollerbach, Kurt Wampler, Jungchul Park, Sangbong Park, Keith Gronlund

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617430

KEYWORDS: Photomasks, Printing, Optical proximity correction, Lithography, Resolution enhancement technologies, Optical lithography, Manufacturing, Calibration, Optics manufacturing, Model-based design

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With immersion and hyper numerical aperture (NA>1) optics apply to the ITRS 2003/4 roadmap scenario (Figure 1); it is very clear that the IC manufacturing has already stepped into the final frontier of optical lithography. Today’s advanced lithography for DRAM/Flash is operating at k₁ close to 0.3. The manufacturing for leading edge logic devices does not follow too far behind. Patterning at near theoretical lithography imaging limit (k₁=0.25) even with hyper NA optics, the attainable aerial image contrast is marginal at best for the critical feature. Thus, one of the key objectives for low k₁ lithography is to ensure the printing performance of critical features for manufacturing. Resolution enhancement technology (RET) mask in combination with hyper NA and illumination optimization is one primary candidate to enable lithography manufacturing at very low k₁ factor. The use of rule-based Scattering Bars (SB) for all types of phase-shifting masks has become the de facto OPC standard since 180nm node. Model-based SB OPC method derives from interference mapping lithography (IML) has shown impressive printing result for both clear (gate) and dark field (contact and via) mask types. There are four basic types of RET mask candidates for 65nm node, namely, alternating phase-shifting mask (altPSM), attenuated PSM (attPSM), chromeless phase lithography (CPL) PSM, and double dipole lithography (DDL) using binary chrome mask. The wafer printing performances from CPL and DDL have proven both are strong candidates for 45nm nodes. One concern for using RET masks to target 45 nm nodes is likely to be the scaling for SB dimension for 4X mask. To assist imaging effectively with high NA, SB cannot be too small in width. However, for SB to be larger than sub-resolution, they can easily cause unwanted SB printing. The other major concern is the unwanted side lobe printing. This may occur for semi-dense pitch ranges under high NA and strong off-axis-illumination (OAI). Looking ahead, for manufacturing at 45 nm and 32nm nodes, one challenge is to break through the so-called k₁ barrier (0.25). Multiple exposure schemes in conjunction with RET masks is our proposed solution

Proceedings Article | 28 June 2005 Paper

Precision process calibration and CD predictions for low-k1 lithography

Ting Chen, Sangbong Park, Gabriel Berger, Tamer Coskun, Joep de Vocht, Fung Chen, Linda Yu, Stephen Hsu, Doug van den Broeke, Robert Socha, Jungchul Park, Keith Gronlund, Todd Davis, Vince Plachecki, Tom Harris, Steve Hansen, Chuck Lambson

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617218

KEYWORDS: Calibration, 3D modeling, Process modeling, Data modeling, Diffusion, Photoresist processing, Lithography, Critical dimension metrology, Photomasks, Semiconducting wafers

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Leading resist calibration for sub-0.3 k₁ lithography demands accuracy <2nm for CD through pitch. An accurately calibrated resist process is the prerequisite for establishing production-worthy manufacturing under extreme low k₁. From an integrated imaging point of view, the following key components must be simultaneously considered during the calibration - high numerical aperture (NA>0.8) imaging characteristics, customized illuminations (measured vs. modeled pupil profiles), resolution enhancement technology (RET) mask with OPC, reticle metrology, and resist thin film substrate. For imaging at NA approaching unity, polarized illumination can impact significantly the contrast formation in the resist film stack, and therefore it is an important factor to consider in the CD-based resist calibration. For aggressive DRAM memory core designs at k₁<0.3, pattern-specific illumination optimization has proven to be critical for achieving the required imaging performance. Various optimization techniques from source profile optimization with fixed mask design to the combined source and mask optimization have been considered for customer designs and available imaging capabilities. For successful low-k₁ process development, verification of the optimization results can only be made with a sufficiently tunable resist model that can predicate the wafer printing accurately under various optimized process settings. We have developed, for resist patterning under aggressive low-k₁ conditions, a novel 3D diffusion model equipped with double-Gaussian convolution in each dimension. Resist calibration with the new diffusion model has demonstrated a fitness and CD predication accuracy that rival or outperform the traditional 3D physical resist models. In this work, we describe our empirical approach to achieving the nm-scale precision for advanced lithography process calibrations, using either measured 1D CD through-pitch or 2D memory core patterns. We show that for ArF imaging, the current resist development and diffusion modeling can readily achieve ~1-2nm max CD errors for common 1D through-pitch and aggressive 2D memory core resist patterns. Sensitivities of the calibrated models to various process parameters are analyzed, including the comparison between the measured and modeled (Gaussian or GRAIL) pupil profiles. We also report our preliminary calibration results under selected polarized illumination conditions.

Proceedings Article | 5 May 2005 Paper

Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes

Song Li, Ting Chen, Santosh Shah, Ketan Joshi, Kalyan Thumaty, Narain Arora

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.601421

KEYWORDS: Fiber optic illuminators, Optical proximity correction, Metals, Critical dimension metrology, Computer architecture, Resistance, Lithography, Lithographic illumination, Resolution enhancement technologies, Manufacturing

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Proceedings Article | 5 May 2005 Paper

Lithography yield check for IC design

Lynn Cai, Ting Chen

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600636

KEYWORDS: Optical proximity correction, Lithography, Resolution enhancement technologies, Silicon, Photomasks, Yield improvement, Manufacturing, Semiconducting wafers, Imaging systems, Semiconductors

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SPIE Journal Paper | 1 April 2005

Extending aggressive low-k1 design rule requirements for 90 and 65 nm nodes via simultaneous optimization of numerical aperture, illumination and optical proximity correction

Sabita Roy, Douglas Van Den Broeke, J. Fung Chen, Armin Liebchen, Ting Chen, Stephen Hsu, Xuelong Shi, Robert Socha

JM3, Vol. 4, Issue 02, 023003, (April 2005) https://doi.org/10.1117/12.10.1117/1.1898244

KEYWORDS: Optical proximity correction, Diffractive optical elements, Critical dimension metrology, Calibration, Photomasks, Stanford Linear Collider, Fiber optic illuminators, Lithography, Printing, Logic

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Proceedings Article | 6 December 2004 Paper

Resist model calibration using 2D developed patterns for low-k1 process optimization and wafer printing predictions

Ting Chen, Douglas Van Den Broeke, Sean Park, Armin Liebchen, J. Fung Chen, Stephen Hsu, Jung Chul Park, Linda Yu, Keith Gronlund

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.568671

KEYWORDS: Calibration, Cadmium, Photoresist processing, Diffusion, Scanning electron microscopy, Semiconducting wafers, Printing, Absorption, Optimization (mathematics), Lithography

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Proceedings Article | 3 May 2004 Paper

Extending aggressive low-k1 design rule requirements for 90-nm and 65-nm nodes via simultaneous optimization of NA, illumination, and OPC

Sabita Roy, Douglas Van Den Broeke, J. Chen, Armin Liebchen, Ting Chen, Stephen Hsu, Xuelong Shi, Robert Socha

Proceedings Volume 5379, (2004) https://doi.org/10.1117/12.536982

KEYWORDS: Diffractive optical elements, Optical proximity correction, Calibration, Critical dimension metrology, Stanford Linear Collider, Photomasks, Fiber optic illuminators, Printing, Logic, Lithography

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Under low-k₁ patterning constraints, it has been a challenge for the lithography process to meet the aggressive IC design rule requirements for the 90nm and the upcoming 65nm nodes. From the imaging perspective, we see the geometric design rules are largely governed by numerical aperture (NA), illumination settings, and OPC for any resolution enhancement technique (RET) applied mask. We report a case study of exploring a set of process feasible design rule criteria based on a state-of-the-art μProcessor chip that contains three different styles of circuit design - standard library cell (SLC), random logic (RML), and SRAM. To keep the packing density higher for SRAM, the critical criteria for design rules involve achievable minimum pitch, sufficient area of contact-landing pad, minimum line end shortening (LES) to ensure poly endcap, and preferably to have optimum pitch for the placement of Scattering Bars (SB). For RML, the goal is to achieve the printing of ever smaller critical dimension (CD) with a greater CD uniformity control. The SLC should be designed to be comparable with both RML and SRAM devices. Hence, the design rule constraints for CD, space, line end, minimum pitch, and SB placement for SLC cell is critically confined. Unlike the traditional method of assuming a linear scaling for the design rule set, we explore achievable design rule criteria for very low k₁ imaging by simultaneously optimizing NA, illumination settings, and OPC (for the optimum placement of SB) for a calibrated process. This is done by analyzing the CD control and the maximum overlapped process window for critical lines, spaces, line ends, and with the respective k₁ factor for the three types of circuits. For 90nm node with k₁ as low as 0.36, a feasible set of design rules for the μProcessor chip can be obtained using 6% attPSM with 6% exposure latitude at 400nm of overlapped depth of focus. Using the similar approach for the scaled down 65nm 6% attPSM, it resulted inadequate process latitude under a set of desired design rule constraints for critical pitch, CD, line end, minimum space, and SB placement. Hence for 65nm case, a CPL mask was used instead, as CPL (100% transmission) has the inherent capability of printing very thin line. The critical design rule criteria for SRAM, RML and SLC were revisited to ensure a large enough process margin.

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