The design flow of Analog and Mixed Signal has to be improved. In a specific application, we propose a definition of the
IP content and the structure of an IP-based library. The case study consists in the neuron-level integration of a complete
system that emulates spiking neural networks. As it is often the case, the development of the analog part of the system
requires the largest amount of time, due to the lack of formalism and automation in that domain. One solution to
accelerate the analog design cycle is to re-use already designed blocks and accumulated design knowledge, which could
be illustrated by the IP (Intellectual Property) concept. Indeed, an experience of about ten years and 19 designed ASICs
allow now to have an accurate idea of the system hierarchy and the recurrent analog blocks, which is the basis of IP-based
design. We will describe the IP-based library which has been developed for that specific application domain and
show how it can be used to accelerate the design cycle of the next ASIC generation.
This paper proposes a CMOS resizing methodology for analog circuits during a technology migration. The scaling rules
aim to be easy to apply and are based on the simplest MOS transistor model. The principle is to transpose one circuit
topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate
the new transistor dimensions. Furthermore, when the target technology has smaller minimum length, we expect to
obtain a decrease of area. This methodology is applied to both linear and non-linear examples: an OTA and a ring
oscillator. The results are compared on three CMOS processes whose minimum length is 0.8 μm, 0.35 μm, 0.25 μm.
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