In order to meet the industry’s increasingly demanding requirements, especially in the area of improving pattern edge placement error for multiple patterning processes, we have developed the leading edge NSR-S635E ArF immersion scanner. The NSR-S635E delivers marked enhancements in scanner performance compared to the previous generation system, and provides expanded alignment capacity with a groundbreaking system called the inline Alignment Station (iAS) [1]. In this paper, we introduce the details of the NSR-S635E, including iAS, and demonstrate their capabilities for solving production challenges now and in the future.
One of the main components of an On-Product Overlay (OPO) error budget is the process induced wafer error. This necessitates wafer-to-wafer correction in order to optimize overlay accuracy. This paper introduces the Litho Booster (LB), standalone alignment station as a solution to improving OPO. LB can execute high speed alignment measurements without throughput (THP) loss. LB can be installed in any lithography process control loop as a metrology tool, and is then able to provide feed-forward (FF) corrections to the scanners. In this paper, the detailed LB design is described and basic LB performance and OPO improvement is demonstrated. Litho Booster’s extendibility and applicability as a solution for next generation manufacturing accuracy and productivity challenges are also outlined
The final lithography accuracy is determined by what is known as the “on-product” performance, which includes product
wafer-related errors and long-term stability. It is evident that on-product performance improvement is absolutely
imperative now, and will become even more crucial in coming years. In order to meet customers’ future requirements,
we have developed the next-generation lithography system focusing on wafer alignment advancements to improve onproduct
performance.
This newly developed wafer alignment system will help customers achieve their aggressive next-generation
manufacturing accuracy and productivity requirements. In this paper, we describe the details of the new wafer
measurement system and provide supporting performance data.
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