Ms. Ushasree Katakamsetty Profile

Ushasree Katakamsetty

SMTS at GlobalFoundries Singapore Pte Ltd

SPIE Involvement:

Author

Area of Expertise:

Place and Route , Design for Manufacturing (DFM) , Fill , Static Timing Analysis , CMP , DRC

Broad experience in various aspects of physical place & route, low power, design rule development, physical verification, DFM, test chip design and semiconductor process development

Specialties:
. Physical Place & Route with low power features, RTL-GDS flow
. Hands on experience on all major EDA tools used for VLSI chip design
. PEX, Static timing analysis and Physical verification DRC & LVS
. DFM Rule based and Model based up to the advanced process nodes of 14nm
. Testchip design, layout, testing methodology, metrology data collection and analysis
. CMP modeling, Fill synthesis, Manufacturability weak points analysis and fixing

Proceedings Article | 26 May 2022 Presentation + Paper

Wafer level analysis and simulation of back end of line chemical mechanical polishing processes

Ushasree Katakamsetty, Stefan Nikolaev Voykov, Sascha Bott, Sam Nakagawa, Tamba Tugbawa, Aaron Gower-Hall, Brian Lee, Jansen Chee, Henry Geng, Weiyang Zhu, Bifeng Li, Kimiko Ichikawa

Proceedings Volume 12052, 1205212 (2022) https://doi.org/10.1117/12.2616078

KEYWORDS: Chemical mechanical planarization, Semiconducting wafers, Data modeling, Calibration, Dysprosium, Back end of line, Polishing, Design for manufacturing, Metals, Chemical reactions

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Proceedings Article | 22 February 2021 Presentation + Paper

Guard-banding of IP against topography sensitivity using silicon-calibrated CMP model

Ushasree Katakamsetty, Sam Nakagawa, Ernesto Gene de la Garza, Ruben Ghulghazaryan, Davit Piliposyan, Simon Favre, Jeff Wilson

Proceedings Volume 11614, 116140Y (2021) https://doi.org/10.1117/12.2585488

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In semiconductor manufacturing, intellectual property (IP) cores/blocks play a dominant role in modern chip design. The driving factor for IP usage is the time-to-market benefit delivered through design reuse. Today, IP blocks include the entire range of modules, ranging from standard cells, memories, and I/O devices to CPUs. Chip designers need complex IP blocks because modern levels of integration allow chips to be a complete system on chip (SOC), not just components of systems. However, as chips become more complex, IP blocks are subject to more interactions from multiple neighboring modules in the chip. Current IP block quality assurance (QA) flows focus mainly on functional verification, performance verification, and design rule checking (DRC). The standard DRC deck checks for minimum and maximum density rules within the IP block. However, when an IP is placed in an SOC, it may encounter complex surrounding scenarios, as when a low density IP is placed next to a higher density area. During integrated circuit (IC) manufacturing, the resulting proximity effects may cause failures or electrical targeting mismatches within the IP, due to etch micro-loading and long-range CMP interactions. Designers can only locate these chemical mechanical polishing (CMP) hotspots related to IP placement in the SOC near the end of the design flow, which limits any floorplan changes to fix the hotspots. Standalone IP block QA is insufficient to detect possible layout- or floorplan-induced problems that can affect manufacturing. In this paper, we present a CMP modeling methodology to guard-band IP against topography variations that can occur after IP placement in the SOC design. We emulate low, average, and high-density scenarios surrounding the IP blocks, followed by CMP simulations and hotspot detection using silicon-calibrated CMP models. After simulation, guidelines provided to fix these CMP hotspots surrounding the IP blocks during early design stages to improve manufacturability and yield. This flow will make IPs robust from CMP hotspots that typically appear after SOC floorplanning.

Proceedings Article | 20 March 2019 Paper

Multilayer CMP hotspot modeling through deep learning

Luis Francisco, Rui Mao, Ushasree Katakamsetty, Piyush Verma, Robert Pack

Proceedings Volume 10962, 109620U (2019) https://doi.org/10.1117/12.2514467

KEYWORDS: Data modeling, Chemical mechanical planarization, Statistical modeling, Performance modeling, Feature extraction, Lithography, Metals, Machine learning, Calibration, Design for manufacturing

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Proceedings Article | 28 March 2017 Presentation + Paper

Cutting-edge CMP modeling for front-end-of-line (FEOL) and full stack hotspot detection for advanced technologies

Ushasree Katakamsetty, Jiansheng Jansen Chee, Yongfu Li, Chiu Wing Hui, Yaodong Huang, Ernesto Gene de la Garza

Proceedings Volume 10148, 101480Q (2017) https://doi.org/10.1117/12.2262076

KEYWORDS: Chemical mechanical planarization, Front end of line, Metrology, Back end of line, Calibration, Silicon, Data modeling, Metals, Manufacturing, Oxides

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Proceedings Article | 16 March 2016 Paper

Hotspot detection and removal flow using multi-level silicon-calibrated CMP models

Ushasree Katakamsetty, Jansen Chee, Yongfu Li, Colin Hui, Jaime Bravo, Tamba Gbondo-Tugbawa, Brian Lee, Kuang-Han Chen, Aaron Gower-Hall, Sang-Min Han

Proceedings Volume 9781, 97810K (2016) https://doi.org/10.1117/12.2219545

KEYWORDS: Chemical mechanical planarization, Manufacturing, Design for manufacturability, Semiconducting wafers, Silicon, Etching, Product engineering, Design for manufacturing, Data modeling, Calibration, Copper, Back end of line, Metals

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Proceedings Article | 4 September 2015 Paper

OPC verification considering CMP induced topography

Rakesh Kumar Kuncha, Aravind Narayana Samy, Ushasree Katakamsetty

Proceedings Volume 9661, 96610E (2015) https://doi.org/10.1117/12.2196646

KEYWORDS: Optical proximity correction, Chemical mechanical planarization, Semiconducting wafers, Lithography, Metals, Finite element methods, Photomasks, Resolution enhancement technologies, Surface finishing, Data modeling

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Proceedings Article | 18 March 2015 Paper

Topography aware DFM rule based scoring for silicon yield modeling

Vikas Tripathi, Ushasree Katakamsetty, Sky Yeo, Colin Hui

Proceedings Volume 9427, 94270V (2015) https://doi.org/10.1117/12.2085733

KEYWORDS: Design for manufacturing, Chemical mechanical planarization, Silicon, Manufacturing, Failure analysis, Design for manufacturability, Metals, Chemical analysis, Lithography, Nanoimprint lithography

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Proceedings Article | 18 March 2015 Paper

20nm CMP model calibration with optimized metrology data and CMP model applications

Ushasree Katakamsetty, Dinesh Koli, Sky Yeo, Colin Hui, Ruben Ghulghazaryan, Burak Aytuna, Jeff Wilson

Proceedings Volume 9427, 94270U (2015) https://doi.org/10.1117/12.2085728

KEYWORDS: Chemical mechanical planarization, Data modeling, Metrology, Semiconducting wafers, Calibration, Manufacturing, Visualization, Metals, Polishing, Surface finishing

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Proceedings Article | 28 March 2014 Paper

Scanner correction capabilities aware CMP lithography hotspot analysis

Ushasree Katakamsetty, Hui Colin, Sky Yeo, Perez Valerio, Yang Qing, Quek Shyue Fong, Narayana Samy Aravind, Ruhm Matthias, Schiwon Roberto

Proceedings Volume 9053, 905312 (2014) https://doi.org/10.1117/12.2053035

KEYWORDS: Lithography, Chemical mechanical planarization, Scanners, Manufacturing, Design for manufacturability, Design for manufacturing, Surface finishing, Copper, Semiconducting wafers, Finite element methods

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Proceedings Article | 1 October 2013 Paper

Challenges in process marginality for advanced technology nodes and tackling its contributors

Aravind Narayana Samy, Roberto Schiwon, Rolf Seltmann, Frank Kahlenberg, Ushasree Katakamsetty

Proceedings Volume 8886, 888609 (2013) https://doi.org/10.1117/12.2047086

KEYWORDS: 3D modeling, Photomasks, Chemical mechanical planarization, Semiconducting wafers, Lithography, Calibration, Finite element methods, 3D metrology, Computer simulations, Reticles

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Proceedings Article | 13 March 2009 Paper

Timing-aware metal fill for optimized timing impact and uniformity

Usha Katakamsetty, Colin Hui, Li-Da Huang, Lannie Weng, Peter Wu

Proceedings Volume 7275, 72751P (2009) https://doi.org/10.1117/12.816476

KEYWORDS: Metals, Copper, Chemical mechanical planarization, Surface finishing, Clocks, Silicon, Calibration, Information operations, Semiconductor manufacturing, Capacitance

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Proceedings Article | 13 March 2009 Paper

Hotspot detection and design recommendation using silicon calibrated CMP model

Colin Hui, Xian Bin Wang, Haigou Huang, Ushasree Katakamsetty, Laertis Economikos, Mohammed Fayaz, Stephen Greco, Xiang Hua, Subramanian Jayathi, Chi-Min Yuan, Song Li, Vikas Mehrotra, Kuang Han Chen, Tamba Gbondo-Tugbawa, Taber Smith

Proceedings Volume 7275, 72751R (2009) https://doi.org/10.1117/12.816556

KEYWORDS: Chemical mechanical planarization, Metals, Copper, Calibration, Data modeling, Manufacturing, Process modeling, Model-based design, Silicon, Physics

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