Dr. Vidya Vaenkatesan Profile

Dr. Vidya Vaenkatesan

System Engineer at ASML Netherlands BV

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Author

Publications (14)

Proceedings Article | 12 November 2024 Presentation + Paper

LCDU decomposition and scaling: mask and resist effects on local MEEF and stochastics

Dominykas Gustas, Sam Borman, Dorothe Oorschot, Joost Bekaert, Hilbert Van Loo, Frank Horsten, Vidya Vaenkatesan, Alberto Colina, Tasja van Rhee

Proceedings Volume 13215, 132150Q (2024) https://doi.org/10.1117/12.3034695

KEYWORDS: Scanning electron microscopy, Stochastic processes, Semiconducting wafers, Reticles, Critical dimension metrology, Reflectivity, Metrology, Lithography, Scanners, Data modeling

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Proceedings Article | 12 November 2024 Presentation + Paper

Enhancing lithography precision: characterizing resist profiles in semiconductor manufacturing with rapid probe microscopy

L. Feng, V. Panchal, R. Thorogate, J. Robinson, J. Cossins, A. D. Humphris, V. Vaenkatesan, J. Finders

Proceedings Volume 13215, 132150A (2024) https://doi.org/10.1117/12.3034551

KEYWORDS: Critical dimension metrology, Lithography, Matrices, Finite element methods, Coating thickness, Atomic force microscopy, 3D metrology, Semiconductor manufacturing, Microscopy, Metrology

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Proceedings Article | 10 April 2024 Presentation + Paper

Holistic assessment and control of total CDU

Jo Finders, Vidya Vaenkatesan, Luc van Kessel, Ruben Maas, Tasja van Rhee, Varun Kakkar, Dominykas Gustas, Eelco van Setten, Claire van Lare

Proceedings Volume 12953, 1295303 (2024) https://doi.org/10.1117/12.3010890

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Reticles, Scanners, Extreme ultraviolet lithography, Atomic force microscopy, 3D mask effects, Monte Carlo methods, Metrology, Simulations

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Proceedings Article | 28 April 2023 Presentation + Paper

Mask roughness contribution to wafer edge placement error

Andreas Frommhold, Joern-Holger Franke, Tatiana Kovalevich, Eelco Van Setten, Vidya Vaenkatesan

Proceedings Volume 12494, 1249408 (2023) https://doi.org/10.1117/12.2658332

KEYWORDS: Speckle, Simulations, Extreme ultraviolet, Metrology, Critical dimension metrology, Edge roughness

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Proceedings Article | 26 February 2021 Presentation + Paper

Statistical analysis of the impact of 2D reticle variability on wafer variability in advanced EUV nodes using large-scale Monte Carlo simulations

Adam Lyons, Luke Long, Tom Wallow, Chris Spence, Ton Kiers, Paul van Adrichem, Vidya Vaenkatesan, Jiyou Fu, Christoph Hennerkes, Cyrus Tabery

Proceedings Volume 11609, 116090C (2021) https://doi.org/10.1117/12.2584744

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Proceedings Article | 27 June 2019 Paper

Evaluation of local CD and placement distribution on EUV mask and its impact on wafer

Vidya Vaenkatesan, Paul van Adrichem, Marleen Kooiman, Michael Kubis, Lieve van Look , Andreas Frommhold, Emily Gallagher, DS Nam, Jan Mulkens

Proceedings Volume 11178, 1117807 (2019) https://doi.org/10.1117/12.2538243

KEYWORDS: Photomasks, Semiconducting wafers, Critical dimension metrology, Metrology, Extreme ultraviolet, Stochastic processes

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Proceedings Article | 18 October 2018 Presentation + Paper

E-beam based EUV mask characterization for studying mask induced wafer effects

Vidya Vaenkatesan, Qing Tian, Emily Gallagher, Jim Wiley, Jo Finders, Michael Kubis, Jan Mulkens, Chiyan Kuan, Kevin Gao

Proceedings Volume 10810, 108100U (2018) https://doi.org/10.1117/12.2502588

KEYWORDS: Photomasks, Semiconducting wafers, Critical dimension metrology, Liquid phase epitaxy, Extreme ultraviolet, Metrology, Cadmium sulfide, Nanoimprint lithography, Inspection, Error analysis

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Proceedings Article | 26 September 2016 Paper

YieldStar based reticle 3D measurements and its application

Vidya Vaenkatesan, Jo Finders, Peter ten Berge, Reinder Plug, Anko Sijben, Twan Schellekens, Harm Dillen, Wojciech Pocobiej, Vasco Jorge, Jurgen van Dijck

Proceedings Volume 9985, 99850M (2016) https://doi.org/10.1117/12.2242857

KEYWORDS: Reticles, Critical dimension metrology, 3D metrology, Photomasks, Metrology, Semiconducting wafers, Extreme ultraviolet, Scanning electron microscopy, EUV optics, Wafer-level optics

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Proceedings Article | 4 September 2015 Paper

YieldStar based reticle 3D measurements and its application

Vidya Vaenkatesan, Twan Schellekens, Natalia Davydova, Harm Dillen, Joep van Dijk

Proceedings Volume 9661, 96610N (2015) https://doi.org/10.1117/12.2196665

KEYWORDS: Reticles, Semiconducting wafers, Critical dimension metrology, Extreme ultraviolet, 3D modeling, Ions, Resolution enhancement technologies, 3D metrology, Metrology, Scanners

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Proceedings Article | 4 September 2015 Paper

Understanding of Out-of-Band DUV light in EUV lithography: controlling impact on imaging and mitigation strategies

N. Davydova, R. Kottumakulal, J. Hageman, J. McNamara, R. Hoefnagels, V. Vaenkatesan, A. van Dijk, K. Ricken, L. de Winter, R. de Kruif, R. Jonckheere, T. Hollink, G. Schiffelers, E. van Setten, P. Colsters, W. Liebregts, R. Pellens, J. van Dijk

Proceedings Volume 9661, 96610B (2015) https://doi.org/10.1117/12.2195733

KEYWORDS: Aluminum, Deep ultraviolet, Reflectivity, Reticles, Semiconducting wafers, Scanners, Extreme ultraviolet, Extreme ultraviolet lithography, Coating, Reflection

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EUV sources emit a broad band DUV Out-of-Band (OOB) light, in particular, in the wavelength range 100-400 nm. This can cause additional exposure of EUV resists made that are based on a ArF/KrF resist platform. This DUV light is partially suppressed while travelling through the optical path but a non-negligible part of it reaches wafer level and impacts imaging.

This is important for imaging at the edges of an image field when fields are printed very close to each other on the wafer (so-called butted fields, with zero field to field spacing). DUV light is reflected from the reticle black border (BB) into a neighboring exposure field on the wafer. This results in a CD change at the edges and in the corners of the fields and therefore has an impact on CD uniformity. Experimental CDU results are shown for 16 nm dense lines (DL) and 20 nm isolated spaces (IS) (N7 logic design features) in the fields exposed at 0 mm and 0.5mm distance on the wafer. Areas close to the edge of the image field are important for customer applications as they often contain qualification and monitoring structures; in addition, limited imaging capabilities in this area may result in loss of usable wafer space.

In order to understand and control OOB DUV light, it must be measured in the scanner. DUV measurements are performed in resist using a special OOB reticle coated with Aluminum (Al) having low EUV reflectance and high DUV reflectance. A model for DUV light impact on the imaging is proposed and verified. For this, DUV reflectance data is collected in the wavelengths range 100-400 nm for Al and BB and the ratio of reflectances of these materials is determined for assumed scanner and resist OOB spectra. Also direct BB OOB test is performed on the wafer and compared to Al OOB results. The sensitivity of 16 nm DL and 20 nm IS to OOB light is experimentally determined by means of double exposure test: a wafer with exposed imaging structures undergoes a second flood exposure from a DUV reflective material (Al or BB).

Finally, several OOB mitigation strategies are discussed, in particular, suppression of DUV light in the scanner (~3x improvement), recent successes of DUV suppression for 16 nm imaging resist (~1.8x improvement) and DUV reflectance mitigation in the reticle black border (~3.8x). An overview of OOB test results for multiple NXE systems will be shown including systems with new NXE:3350 optics with improved OOB suppression.

Proceedings Article | 13 March 2015 Paper

Overlay and edge placement control strategies for the 7nm node using EUV and ArF lithography

Jan Mulkens, Michael Hanna, Hannah Wei, Vidya Vaenkatesan, Henry Megens, Daan Slotboom

Proceedings Volume 9422, 94221Q (2015) https://doi.org/10.1117/12.2085761

KEYWORDS: Scanners, Overlay metrology, Extreme ultraviolet lithography, Optical lithography, Semiconducting wafers, Lithography, Metrology, Critical dimension metrology, Extreme ultraviolet, Control systems

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Proceedings Article | 8 November 2012 Paper

Impact of an etched EUV mask black border on imaging and overlay

Natalia Davydova, Robert de Kruif, Norihito Fukugami, Shinpei Kondo, Vicky Philipsen, Eelco van Setten, Brid Connolly, Ad Lammers, Vidya Vaenkatesan, John Zimmerman, Noreen Harned

Proceedings Volume 8522, 852206 (2012) https://doi.org/10.1117/12.964547

KEYWORDS: Semiconducting wafers, Reticles, Photomasks, Extreme ultraviolet, Etching, Reflectivity, Deep ultraviolet, Scanning electron microscopy, Optical proximity correction, Extreme ultraviolet lithography

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There are multiple mask parameters that can be tuned to optimize the lithographic performance of the EUV photo mask[1]. One of them is the absorber height. A reduction of the absorber height allows, for example, a higher resolution patterning on mask and reduces the OPC needed for shadowing correction[1][2][5]. Downside of a thinner absorber is the increased reflectivity which manifests itself not only in the image field (contrast loss) but also in the so called light shield area or image border. The image border is a pattern free (absorber covered) area around the die on the photo mask forming the transition area between the part on the mask that is completely shielded from the exposure light by the Reticle Masking (REMA) blades and the die. The image border accommodates the finite REMA placement accuracy and the half shadow of the REMA blades allowing close spaced die printing on the wafer. When printing a die at dense spacing, which is common practice in a production environment, the image border will overlap part of the neighboring die. This causes actinic EUV and DUV out of band light reflection from the image border exposing the overlapped die area and affecting CD and contrast at the edges of the dies. For a 44 nm thick absorber we found a CD impact of 8 nm for 32 nm dense lines[3] whereas for a 55 nm thick absorber the effect was 4 nm for 27 nm dense lines[7]. Increasing the die spacing would prevent this unwanted exposure but results in an unacceptable loss of valuable wafer real estate thereby reducing the yield per wafer and is thus not a viable manufacturing solution. Optical Proximity Correction (OPC) using ASML Brion’s Tachyon NXE model at the edges of the die was proposed as possible solution to this problem[3]. An alternative is to create a so called Black Border: the reflectivity in the image border is reduced to a sufficiently low level by for example increasing the absorber thickness, add a special coating or replace the absorber with a low reflective material[4][5]. The most radical solution is removal of the absorber and the underlying multilayer down to the low reflective substrate, so-called multilayer etching[4][6]. In this paper we will present the effects of such a Black Border created by a multilayer etch on features and their placement on the reticle and the impact on CD of 27 nm dense lines on the wafer. By comparing the wafer CDU printed with and without Black Border we will determine how well the image border effect is mitigated by the multilayer etching.

Proceedings Article | 14 October 2011 Paper

Holistic lithography for EUV: NXE:3100 characterization of first printed wafers using an advanced scanner model and scatterometry

Frank A. J. M. Driessen, Natalia Davydova, J. Jiang, H. Kang, V. Vaenkatesan, D. Oorschot, I. Kim, S. Kang, Y. Lee, J. Yeo, K. Gronlund, H. Liu, K. van Ingen-Schenau, R. Peeters, C. Wagner, J. Zimmermann, O. Schumann

Proceedings Volume 8166, 81660Z (2011) https://doi.org/10.1117/12.898955

KEYWORDS: Semiconducting wafers, Scanners, Photomasks, Lithography, Extreme ultraviolet lithography, Extreme ultraviolet, Reflectivity, Deep ultraviolet, Metrology, Critical dimension metrology

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Proceedings Article | 2 April 2011 Paper

YieldStar: a new metrology platform for advanced lithography control

Jos Maas, Martin Ebert, Kaustuve Bhattacharyya, Hugo Cramer, Arthur Becht, Stefan Keij, Reinder Plug, Andreas Fuchs, Michael Kubis, Tom Hoogenboom, Vidya Vaenkatesan

Proceedings Volume 7985, 79850H (2011) https://doi.org/10.1117/12.896902

KEYWORDS: Semiconducting wafers, Overlay metrology, Lithography, Scanners, Metrology, Critical dimension metrology, Extreme ultraviolet lithography, 3D metrology, Sensors, Data processing

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Showing 5 of 14 publications

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