In this paper, we present a thorough investigation of self-aligned octuple patterning (SAOP) process characteristics, cost structure, integration challenges, and layout decomposition. The statistical characteristics of SAOP CD variations such as multi-modality are analyzed and contributions from various features to CDU and MTT (mean-to-target) budgets are estimated. The gap space is found to have the worst CDU+MTT performance and is used to determine the required overlay accuracy to ensure a satisfactory edge-placement yield of a cut process. Moreover, we propose a 5-mask positive-tone SAOP (pSAOP) process for memory FEOL patterning and a 3-mask negative-tone SAOP (nSAOP) process for logic BEOL patterning. The potential challenges of 2-D SAOP layout decomposition for BEOL applications are identified. Possible decomposition approaches are explored and the functionality of several developed algorithm is verified using 2-D layout examples from Open Cell Library.
Self-aligned multiple patterning (SAMP) techniques can potentially scale integrated circuits down to half-pitch 7nm. In this paper, we present a comparative analysis of self-aligned quadruple (SAQP) and sextuple (SASP) techniques by investigating their technological merits and limitations, process complexity and cost structures, strategy of layout decomposition/synthesis, and yield impacts. It is shown that SASP process complexity is comparable to that of SAQP process, while it offers 50% gain in feature density and may be extended for one more node. The overlay yield of cut process is identified to be a challenge when the minimum device feature is scaled to half-pitch 7nm. The mask design issues for various applications using each technique are discussed, and the corresponding layout decomposition/synthesis strategy for complex 2D patterning is proposed. Although the high-dose EUV single-cut process can save significant costs when applied to replace the 193i multiple-cut process to form fin/gate structures, our cost modeling results show that SADP+EUV approach is still not cost effective for patterning other critical layers that generally require the same mask number (and lithographic steps) as the non-EUV schemes.
A compact model is developed to study the fin-width roughness (FWR) induced device variability and its impacts on FinFET performance. The perturbation theory is applied to obtain the analytic solution to nonlinear Poisson’s equation by treating FWR as a small deviation/perturbation from the ideal (flat) fin boundary. High accuracy of this compact model is verified with TCAD simulations. Both model calculation and TCAD simulation results show that FWR variation significantly affects FinFET device behavior. The conventional short-channel model is inaccurate to describe the FWR effects. Several types of FWR functions are studied and important device parameters such as Vt.sat, Vt.lin, DIBL are extracted from TCAD simulations, all of which are found sensitive to FWR variation.
Self-aligned sextuple patterning (SASP) is a promising technique to scale down the half pitch of IC features to sub- 10nm region. In this paper, the process characteristics and decomposition methods of both positive-tone (pSASP) and negative-tone SASP (nSASP) techniques are discussed, and a variety of decomposition rules are studied. By using a node-grouping method, nSASP layout conflicting graph can be significantly simplified. Graph searching and coloring algorithm is developed for feature/color assignment. We demonstrate that by generating assisting mandrels, nSASP layout decomposition can be degenerated into an nSADP decomposition problem. The proposed decomposition algorithm is successfully verified with several commonly used 2-D layout examples.
Self-aligned quadruple patterning (SAQP) process is a proven technique for deep nano-scale IC manufacturing, while its mask design and layout decomposition strategy is less intuitive. In this paper, we examine both 2- and 3-mask SAQP process characteristics and develop various decomposition methods to achieve higher feature density and 2-D design flexibility. It is demonstrated that by generating assisting mandrels, SAQP layout decomposition can be degenerated into a SADP decomposition problem for which mature algorithms already exist in our EDA industry. Moreover, a spacer-expansion mask concept is introduced and a grouping/coloring algorithm to assign feature colors is developed for 3-mask SAQP layout decomposition. Finally, several 2-D layouts are successfully decomposed, showing the functionality of the decomposition method we proposed.
Self-aligned triple patterning (SATP) technique offers both improved resolution and quasi-2D design flexibility for
scaling integrated circuits down to sub-15nm half pitch. By implementation of active layout decomposition/synthesis
using mandrel and spacer engineering, SATP process represents a prospective trend that not only drives up the feature
density, but also breaks the 1-D gridded limitations posed to future device design. In this paper, we shall present the
research progress made in optimizing SATP process to improve its lithographic performance. To solve the previously
reported difficulties in etching small mandrels and removing sacrificial spacers, new materials are tested and a
promising scheme (using oxide as the mandrel and poly/amorphous Si as the sacrificial spacer) is identified. In the new
process, a diluted HF process is applied to shrink the mandrel (oxide) line CD and a highly selective dry etch (which
does not attack the mandrel and structural spacer) is developed to strip the sacrificial Si spacers, resulting in
significantly improved process performance. We also address the issue of reducing SATP process complexity by exploring the feasibility of a 2-mask concept for specific types of layout.
A hybrid self-aligned triple and negative-tone double patterning (HTDP) technique is proposed to achieve improved
resolution and quasi-2D IC design flexibility at lower cost. Critical challenges of HTDP process and its key design
issues such as overlay, layout decomposition and synthesis are investigated, and possible design solutions are discussed.
It is shown that using mandrel (including assisting mandrel) and spacer engineering, HTDP on-grid layout design is a
promising approach to break the limitation of 1-D gridded design. Efficient formulation of HTDP layout
decomposition/synthesis into a Boolean satisfactory problem is demonstrated. Moreover, by considering geometric
constraints of HTDP layout and several process related assumptions, it is possible to significantly reduce the number of layout features and Boolean input variables. Several examples of 2-D layout are used to demonstrate the process of HTDP decomposition/synthesis, as well as the simplification of its algorithm to reduce runtime. Specifically, preliminary results from implementation of a 2-mask HTDP design for patterning a 2-D dense line/space array with pads are reported.
Spacer based self-aligned multiple patterning (SAMP) techniques potentially allow us to scale integrated circuits down
to sub-10nm half pitch with no need of EUV lithography. In this paper, we shall present a general analysis of
technological merits, process complexity and costs of various SAMP techniques. It is shown that some SAMP
techniques such as self-aligned quadruple/sextuple patterning (SAQP/SASP) are more capable of increasing the pattern
density, while self-aligned triple patterning (SATP) is more beneficial to reducing process complexity by allowing
quasi-2D IC design and requiring fewer masks. Besides their different scaling/resolution capability and process
challenges, each SAMP technique is accompanied with unique characteristics of CD uniformity (CDU) and line-width
roughness (LWR), which indicates their application areas and the related IC design/fabrication methodologies vary
significantly by industry segment. Process costs of various self-aligned multiple patterning schemes are calculated,
which show that within the common resolution capability, SATP technique is the most cost effective while the
EUV+SADP approach only offers limited benefits.
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