Motoya Okazaki, Raymond Maas, Sen-Hou Ko, Yufei Chen, Paul Miller, Mani Thothadri, Manjari Dutta, Chorng-Ping Chang, Abraham Anapolsky, Chris Lazik, Yuri Uritsky, Martin Seamons, Deenesh Padhi, Wendy Yeh, Stephan Sinkwitz, Chris Ngai
The objective of this study was to examine the defect reduction effect of the wafer edge polishing step on the
immersion lithography process. The experimental wafers were processed through a typical front end of line device
manufacturing process and half of the wafers were processed with the wafer edge polishing just prior to the immersion
lithography process. The experimental wafers were then run through two immersion lithography experiments and the
defect adders on these wafers were compared and analyzed. The experimental results indicated a strong effect of the
edge polishing process on reducing the particle migration from the wafer edge region to the wafer surface during the
immersion lithography process.
The extendibility of optical lithography using KrF and ArF exposure tools is still being investigated, even, being demanded strongly now, due to the unforeseen issues, high cost, and general difficulty of NGLs - including F2 and immersion lithography. In spite of these challenges Moore's Law requires continued shrinks and the ITRS roadmap still keeps its aggressive timetable. In order to follow the ITRS roadmap, the resolution must keep improving by increasing the lens NA for optical exposure tools. However, the conventional limit of optical resolution (kpitch=0.5) is very close for the current technologies, perhaps limiting progress unless NGL becomes available quickly. Therefore we need to find a way to overcome this seemingly fundamental limit of optical resolution. In this paper, we propose two practical two-mask /double-exposure schemes for doubling resolution in future lithography. One method uses a Si-containing bi-layer resist, and the other method uses Applied Materials' APF (a removable hard mask). The basic ideas of both methods are similar: The first exposure forms 1:3 ratio L/S patterns in one resist/hard mask layer, then the second exposure images another 1:3 ratio L/S pattern in-between the two lines (or two spaces) formed by the first exposure. The combination of these two exposures can form, in theory, kpitch=0.25 patterns. In this paper, we will demonstrate 70nm L/S pattern (140nm pitch) or smaller by using a NA0.68 KrF Scanner and a strong-RET reticle, which corresponds to kpitch = 0.38 (k1=0.19). We will also investigate the critical alignment and CD control issues for these two-mask/dual-exposure schemes.
A PECVD deposited carbon hardmask is combined with dielectric anti-reflective coating (DARC) for the patterning of sub-90nm lines with 248nm lithography. Using this CVD dual layer stack, <1% reflectivity control is demonstrated for both 248nm and 193nm lithography. The film stack is tested with an etch integration scheme to reduce polysilicon gate critical dimension (CD). The dual layer stack can be defined with less than 100nm thick photoresist. Because of the minimal resist required to open the stack, this film stack enables an integration scheme that extends conventional photoresist trim processes up to 70% of the starting line width. In addition to conventional trim process, a resistless carbon mask trim process is investigated to further shrink the gate critical dimension. The results show that the carbon hardmask has greater than 6:1 etch selectivity to polysilicon, enabling the extension of the resist trimming technique to generate sub-30nm structures using 248nm lithography.
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