KEYWORDS: Sensors, Interference (communication), Electrons, Quantization, Cameras, Mid-IR, Capacitors, Signal detection, Signal processing, Digital signal processing
A digital readout for a 128X128 MWIR imaging spectrometer was developed and demonstrated in a camera system. InSb
detectors were hybridized to the readout and mounted in a ceramic pin grid array package. A second order MOSAD,
Multiplexed OverSample A/D, is placed at each pixel on a 40 um pitch. Double metal CMOS with 0.5 um geometry was
used in the readout design. The sensor is designed to operate at up to 300 ksps. At this rate, depending on decimation,
achievable dynamics ranges are, 14 bits at 4 kfps, 20 bits at 1 kps and 32 bits at 30 fps. Effective well capacity reaches
10E10 electrons at 30 fps decimation. On focal plane power consumption is under 90 milliwatts. A single 3.3 volt power
supply and clock source drive the sensor. All timing and controls are derived on the sensor. The sensor hybrid was
demonstrated in a pour fill dewar with f 2.3 optics. A next generation design can be built on a 10 um pixel pitch with 0.13
um CMOS to support other detector materials with the same or better performance This technology was developed under
a SBIR program sponsored by US Air Force, Arnold Air Force Base.
A large format, area array, digital visible light camera was developed based on A/D conversion at each pixel. Production CMOS technology was used in the development of a monolithic front side illuminated photo diode pixel. Each pixel includes a one loop MOSAD, (Multiplexed Oversample A/D) converter, photo diode, and buffered output to support a very large array format operating at high frame rates. MOSAD is a modification of the delta sigma approach to A/D conversion. The 12 megapixel sensor consists of a 4,000X3,000 pixel array capable of up to 1,000 frames per second sample rate. To approximately fit a 35 millimeter optics format, a pixel size of 8.5 μm was selected. There are no operational amplifiers required at the pixel to perform the A/D function, thus allowing a high fill factor. With this pixel size, a 48% fill factor and 38% photo diode area was achieved. A single process run was completed yielding five 8 inch wafers each containing 27 camera die. The single poly, three metal AMIS 0.35 μm CMOS process was used in the fabrication process. Selected die were directly mounted on a specially designed carrier daughter board. Camera support electronics were designed and fabricated to allow sampling of the camera output using commercial standard Camera Link interfacing. Off the shelf 35 Millimeter optics was used to validate imaging capabilities of the sensor. Tests show that the first iteration sensor chip design works to the fundamental requirements and can image.
The design for a large format digital visible light area array was developed based on A/D conversion at each pixel. Production CMOS technology was used in the development of a monolithic front side illuminated photo diode pixel. Each pixel includes a one loop MOSAD, multiplexed oversample A/D, converter, the photo diode and a buffered output to support a very large array format operating at a high frame rate. MOSAD is a modification of the delta sigma approach to A/D conversion. The requirements are to develop a 4,000 x 3,000 pixel array capable of up to 1,000 frames per second sample rate. A design was developed using the AMIS 0.35 μm CMOS process with a single poly and three metal layers. To approximately fit a 35 millimeter optics format, a pixel size of 8.5 μm was selected. There are no operational amplifiers required at the pixel to perform the A/D function, thus allowing a high fill factor. With this pixel size, a 48% fill factor and 38% photo diode area was achieved. The design can produce a pixel size of 4.3 μm square with the use of 0.18 μm CMOS without sacrificing fill factor. Alternate approaches to satisfy the 1 kiloframe sample rate with up to 10 bits dynamic range were analyzed. The design is still in progress with layout and simulation of the critical elements complete. This development program is sponsored by the Army White Sands Missile Range.
MOSAD(copyright), Multiplexed OverSample Analog to Digital conversion, is a low power on focal plane analog to digital, A/D, process that places an oversample A/D at each pixel site. Two full custom designs for a visible light staring array were developed with this approach. One design approach uses a silicon photo diode in combination with photo gates at the pixel and the other approach uses an all photo gate sensor for detection. Both arrays were designed with a 320x240 format with the pixels placed on 16 micron centers. The system includes the camera assembly, driver interface assembly, a frame grabber board with integrated decimator and Windows 2000 compatible software for real time image display. The camera includes the sensor, either photo gate or photo diode, mounted on a PC card with support electronics. A custom lens mount attaches the camera to C or CS mount lens. Testing was done with a Tamron 13VM2812 CCTV CS mount lens. Both an RS644 and an RS422 parallel interface card assembly was developed to attach to the frame grabber board. The final iteration cameras were tested at the Amain facility and pictures were taken. At 400 samples per second, measured on chip power consumption is under 10 milliwatts. Noise measurements at sample rates from 400 samples per second to 1,600 samples per second were taken for both parts. The photo diode worked and produced images but it had a sense amplifier problem that prevented adequate noise measurement. At 28 times oversample, the photo gate achieved typical 9 to 11 bits signal to noise with best case measured at 13 bits. Nonuniformity variation was below the noise floor.
A digital readout for a 128 by 128 MWIR focal plane using InSb detectors was developed for imaging spectrometry. There are a total of 16,384 oversample A/D converters on the chi p that provide a 14 bit linear data output at a nominal frame rate of 4,000 samples per second. An early prototype design was completed and tested without detectors and found to meet all requirements. A second iteration is in final hybrid assembly for demonstration where it will be mounted in a dewar with optics. The device is designed to work with a 3.3 volt power supply with on chip A/D power consumption of under 50 milliwatts. This technology was developed under a SBIR program sponsored by US Air Force, Arnold Air Force Base.
KEYWORDS: Diodes, Signal to noise ratio, Analog electronics, Capacitors, Switching, Interference (communication), Staring arrays, Data conversion, Clocks, Quantization
A large format prototype infrared camera based on the MOSAD (Multiplexed OverSample A/D converter) concept was developed and demonstrated. Each pixel readout buffer is composed of a two integrator one bit modulator that converts the accumulating photon induced charge to a digital value. This camera is designed around a 640 X 480 pixel focal plane array with an A/D converter at each pixel. The focal plane is a CMOS design readout hybridized to a MWIR (3 - 5 micron) N on P Mercury Cadmium Telluride detector array with pixels placed on 27 micron centers. Amain developed and tested the readout, camera and electronics. Rockwell Science Center provided the detectors which they hybridized to the Amain readout.
On focal plane analog to digital conversion, A/D has matured to such an extent that large low power arrays are now being built. Recently Amain developed a cooled MWIR 640 X 480 staring focal plane array with an A/D at each pixel. The technology, MOSAD$CPY, Multiplexed OverSample A/D, allowed the placement of over 300,000 converters on the focal plane on 27 micron centers with 12 bits dynamic range. A unique one bit digital data format, Stream Vision$CPY, was generated on focal plane and transmitted directly to a Ferroelectric LCD for real time viewing of the IR scene. This data stream produces apparent gray to the eye by rapidly modulating the on/off density of the display pixel in concert with the corresponding pixel on the focal plane array. To correct for detector nonuniformity (NUC), a systolic array of parallel processing elements was developed that provided offset and gain correction while preserving the dynamic range of the Stream Vision data. The benefits of this new digital format is that no transformation is required for processing and displaying the image data and there is no analog electronics in the system. Compared to present displays using either PCM to analog or PCM to pulse width modulation. Stream Vision uses less electronics and substantially lower switching bandwidth for the equivalent dynamic range. This development was sponsored by Naval Air Warfare Center under a Phase II SBIR program.
Future high performance IR imaging system require high density focal planes containing up to one million or more detectors. Technological advances are needed to handle the resulting readout data rates in excess of Gbauds/sec and to minimize the on-focal-plane heat load caused by the currently used drivers and signal carrying cables connecting the focal plane inside the vacuum dewar with the outside signal processor. Optical interconnects are a practical alternative only for digital data because of the high non- linearity of the electrical to optical conversion process. We propose to solve these problems by A/D converting the detector signals on the focal pane (FPA) and using on-focal- plane quantum well light modulators to transform the electrical to optical signals. The latter are transmitted by a light beam from the FPA to the signal processor or the display electronics. The enabling technologies are the recently demonstrated on-focal-plane MOSAD converter achieving 14 bit dynamic range and the quantum well light modulators being develop by Lucent Technologies for highspeed bistable optical switches called SEED's for use in telecommunication. We will demonstrate one optical readout channel servicing 4 columns of a LWIR detector array mounted in an experimental dewar.
KEYWORDS: Interference (communication), Signal to noise ratio, Analog electronics, Sensors, Data conversion, Quantization, Calibration, Switching, Digital filtering, Color imaging
MOSAD, provides a low power on focal pane analog to digital, A/D, process. In this approach, an oversample A/D is placed at each pixel site, with resultant benefits to response linearity and noise performance. An architecture for a visible light imaging sensor using silicon charge well detection was developed for application into video conferencing. There are a total of 76,800 A/D's on the chip. The devise is a monolithic integrated circuit that includes the sensors, A/D's and readout circuitry. A production 1.2 micron CCD/CMOS process was used in it construction. The array was designed with a 320 X 240 format with the pixels placed on 16 micron centers. There was negligible impact on the pixel area due to the A/D such that a fill factor of 67 percent was achieved with front side illumination. On chip power consumption is under 15 milliwatts. Pixels are read in the same manner as accessing the bit locations of a DRAM. As each row of pixels are accessed, they put ones or zeros on the output column that are sensed and passed onto the output buss. The A/D design is based on the patented MOSAD technology, It uses charge well switching at the pixel to convert the accumulated analog signal to digital data. Because of its high noise immunity, no pixel buffer amplifier is required, thus preserving fill factor. Another unique characteristic is the output data format which is directly compatible with Stream Vision, a patented digital display method. This format was adopted to produce a low cost all digital system from camera to display.
Development of per pixel analog to digital conversion technology for staring focal plane arrays has resulted in improvements in well capacity, power consumption, linearity and signal to noise performance compared to present analog readout approaches. This new digital approach has also allowed the application of alternative on focal readout approaches. These include passive optical devices for readout as well as current mode switching wired output. Test results and design considerations of a recently completed 128 X 128 staring array are presented. The design was based on MOSAD, Multiplexed OverSample A/D, which places a filtering A/D modulator at each pixel. This readout has been linked on focal plane to passive reflective optical modulators providing high data rate digital outputs as an alternative to wired interconnect. A comparative study of current mode wired switching verses optical mode readout was completed. These results will also be presented. Both the optical readout and focal plane array designs were developed with funding from the U.S. Army Night Vision and Electronic Sensors Directorate.
The design for a staring focal plane array with on focal plane A/D was developed to support space based sensor applications. Readout interface requirements and noise analysis were completed for an HgCdTe LWIR detector 256 by 256 array with 13.9 micron cutoff operating at 40 K with background of 1011 or less. The Amain developed MOSAD (multiplexed oversample A/D) technology was applied as the readout and focal plane A/D converter with a requirement for 12 bits of conversion accuracy at 100 frames per second, a pixel pitch as small as 30 microns and heat load lower than analog readout. In the analysis of the readout requirements, consideration for SNR, dynamic range, linearity, well capacity, heat dissipation and component total dose drift were included. Conclusions are that greater than 12 bits dynamic range can be supported and that commercial grade microelectronics can be used for the digital readout, requiring only periodic gain calibration to compensate for component aging due to space environmental effects. This work was sponsored by the U.S. Air Force Phillips Laboratory, Albuquerque, New Mexico.
An on focal plane digital readout development suggested by the Army Night Vision & Electronics Sensors Directorate is proceeding under a combined program with the development of two color HCT detector arrays. The on focal plane A/D process is based on the Amain patented multiplexed oversample A/D, MOSAD, technology. In the first year of the program, prototype on focal plane analog to digital converters for both staring arrays and scanning arrays were built and demonstrated. The prototypes included a 2 loop double ended switched MOSAD and a 1 loop single ended MOSAD. Results from the original experimental prototypes showed conclusively that better than 14 bits could be achieved and that well capacity could be increased to support high background HCT needs approaching 109 electrons. In the second year, a 64 X 64 staring array for HCT LWIR detectors, 50 micron centers, was built based on these original prototype designs. The layout of the per pixel MOSAD A/D staring array used Orbit 1.2 micron CMOS process and achieved a pixel size of 40 microns with a well capacity of 1.9 X 108 electrons. Integration capacitors were built using Orbit's normal double poly capacitors with a standard buffered direct inject TIA detector interface configuration. Preliminary testing has been completed indicating complete functionality. Fermionics LWIR HCT detectors with cutoff at 9 microns have been built for attachment to the readout but indium bumping was not completed in time to report system level testing results. However, some noise tests have been performed using on array current mirrors. These tests indicate that better than 12 bits has been achieved, but lower noise current sources will be required for a more accurate measurement.
KEYWORDS: Interference (communication), Signal to noise ratio, Analog electronics, Signal processing, Digital filtering, Sensors, Clocks, Filtering (signal processing), Modulators, Optical filters
Future imaging sensors for the aerospace and commercial video markets will depend on low cost, high speed analog-to-digital (A/D) conversion to efficiently process optical detector signals. Current A/D methods place a heavy burden on system resources, increase noise, and limit the throughput. This paper describes a unique method for incorporating A/D conversion right on the focal plane array. This concept is based on Sigma-Delta sampling, and makes optimum use of the active detector real estate. Combined with modern digital signal processors, such devices will significantly increase data rates off the focal plane. Early conversion to digital format will also decrease the signal susceptibility to noise, lowering the communications bit error rate. Computer modeling of this concept is described, along with results from several simulation runs. A potential application for direct digital conversion is also reviewed. Future uses for this technology could range from scientific instruments to remote sensors, telecommunications gear, medical diagnostic tools, and consumer products.
An on focal plane analog to digital conversion approach has been implemented for infrared sensor application. This development uses a patented oversampling methodology named MOSAD (Multiplexed OverSample Analog to Digital) in the design of simple circuits that can be placed at individual pixel sites. The construction of an analog to digital converter pixel is allowed with this technology. Most of the crosstalk and broadband noise associated with analog multiplexing and readout is avoided. Two demonstration designs were developed and built with Orbit, 1.2 micron CMOS Foresight process. For cost reasons, both designs were placed on the small die, 4.8 X 4.8 mm, and packaged in a 84 pin grid array carrier. These designs consist of a scanning array, 1 X 64 on 60 micron centers and two column portion of a 64 X 64 staring array on 60 micron centers. The detector buffer design will support HgCdTe high background applications. Support for the demonstration was received from Army, Night Vision Laboratory under their two color detector SBIR development program.
The use of a multiple dielectric gate insulator, and the addition of a gate insulator extension and guard-bars to the NMOS transistors, has resulted in a significant increase in total-dose ionizing radiation resistance for CMOS IR readout multiplexer circuits operating at cryogenic temperatures. This paper describes the implementation of these modifications, and also some observed anomalous transistor offset voltages that were apparently due to charges trapped in the multiple dielectric gate insulator during the circuit fabrication process.
A program to upgrade the test capability for JR focal plane arrays and readouts is in progress at Aerojet. The objective of the development is to reduce the number and complexity of the steps in the test process, reduce in socket test time and provide a simplified set up procedure for production testing. There are two areas of study in the program. One is concerned with examining multiple fabrication sources for readout circuits. Cooperative studies are being performed with Orbit Semiconductor, Harris Semiconductor, TRW, UTMC, and Matra (France). Temperature profiles of noise performance, threshold variation, gain and subthreshold operation are being developed for several different manufacturers. The objective is to determine the feasibility of eliminating all cryogenic testing for sorting of readouts before final hybrid assembly thus reducing test steps. The second area of development, which will be discussed in this paper, is the application of a commercially available automated test system for production testing and engineering characterization ofreadouts and focal plane arrays. The Sentry Series 80 mixed signal tester is being fixtured for low noise measurements and interfacing to dewars for cryogenic testing. The multiuser foregroundlbackground operating system software has the advantage of allowing noise and other statistical calculations to be performed in the background without impeding test measurements. It also has the advantage in production of requiring no manual instrumentation set up or interconnect. The improvements in test throughput and analysis capability will be shown in adapting this class of tester as opposed to assembling test instruments in a custom made computer controlled test approach
KEYWORDS: Modulators, Sensors, Analog electronics, Digital filtering, Interference (communication), Signal processing, Infrared radiation, Digital electronics, Digital signal processing, Electronic filtering
It is generally accepted that sensor systems can benefit from some form of on-focal-plane A/D conversion in terms of overall system noise improvement. The issue of whether or not the Delta-Sigma modulation process can be applied to the development of an approach using conventional A/D converters or cryogenic circuit materials is addressed from the standpoint of the scanning focal plane. Each pixel row of the scanning sensor is treated as a continuous analog signal source with a fixed signal bandwidth. By allocating a Delta-Sigma converter per sensor pixel row, theory predicts the oversample rate required to achieve the designed conversion resolution. The Delta-Sigma consists of two major parts. The modulator, which samples the analog input and develops a corresponding digital bit stream, and the digital signal processor, which compresses the bit stream into the Nyquist rate multibit codes and performs noise filtering, are described. Only the modulator needs to be on the focal plane since its output is digital. This reduces the development problem to one of fitting the modulator only into the allocated space and power budget per sensor.
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