Ms. Xue Li Profile

Xue Li

at Semiconductor Manufacturing International Corp

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Publications (4)

Proceedings Article | 20 March 2018 Paper

An efficient way of layout processing based on calibre DRC and pattern matching for defects inspection application

Helen Li, Robben Lee, Tyzy Lee, Teddy Xue, Hermes Liu, Hall Wu, Qijian Wan, Chunshan Du, Xinyi Hu, Zhengfang Liu

Proceedings Volume 10588, 105880Y (2018) https://doi.org/10.1117/12.2297349

KEYWORDS: Defect inspection, Inspection equipment, Defect detection, Scanners

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As technology advances, escalating layout design complexity and chip size make defect inspection becomes more challenging than ever before. The YE (Yield Enhancement) engineers are seeking for an efficient strategy to ensure accuracy without suffering running time. A smart way is to set different resolutions for different pattern structures, for examples, logic pattern areas have a higher scan resolution while the dummy areas have a lower resolution, SRAM area may have another different resolution. This can significantly reduce the scan processing time meanwhile the accuracy does not suffer. Due to the limitation of the inspection equipment, the layout must be processed in order to output the Care Area marker in line with the requirement of the equipment, for instance, the marker shapes must be rectangle and the number of the rectangle shapes should be as small as possible. The challenge is how to select the different Care Areas by pattern structures, merge the areas efficiently and then partition them into pieces of rectangle shapes. This paper presents a solution based on Calibre DRC and Pattern Matching. Calibre equation-based DRC is a powerful layout processing engine and Calibre Pattern Matching’s automated visual capture capability enables designers to define these geometries as layout patterns and store them in libraries which can be re-used in multiple design layouts. Pattern Matching simplifies the description of very complex relationships between pattern shapes efficiently and accurately. Pattern matching’s true power is on display when it is integrated with normal DRC deck. In this application of defects inspection, we first run Calibre DRC to get rule based Care Area then use Calibre Pattern Matching’s automated pattern capture capability to capture Care Area shapes which need a higher scan resolution with a tune able pattern halo. In the pattern matching step, when the patterns are matched, a bounding box marker will be output to identify the high resolution area. The equation-based DRC and Pattern Matching effectively work together for different scan phases.

Proceedings Article | 16 March 2016 Paper

Characterization of shallow trench isolation CMP process and its application

Helen Li, ChunLei Zhang, JinBing Liu, ZhengFang Liu, Kuang Han Chen, Tamba Gbondo-Tugbawa, Hua Ding, Flora Li, Brian Lee, Aaron Gower-Hall, Yang-Chih Chiu

Proceedings Volume 9781, 978113 (2016) https://doi.org/10.1117/12.2219912

KEYWORDS: Chemical mechanical planarization, Front end of line, Back end of line, 3D modeling, Design for manufacturing, Process modeling, Manufacturing, Process engineering, Transistors, Copper, Calibration, Oxides, Data modeling, Polishing

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Chemical mechanical polishing (CMP) has been a critical enabling technology in shallow trench isolation (STI), which is used in current integrated circuit fabrication process to accomplish device isolation. Excessive dishing and erosion in STI CMP processes, however, create device yield concerns. This paper proposes characterization and modeling techniques to address a variety of concerns in STI CMP. In the past, majority of CMP publications have been addressed on interconnect layers in backend- of-line (BEOL) process. However, the number of CMP steps in front-end-of-line (FEOL) has been increasing in more advanced process techniques like 3D-FinFET and replacement metal gate, as a results incoming topography induced by FEOL CMP steps can no longer be ignored as the topography accumulates and stacks up across multiple CMP steps and eventually propagating to BEOL layers. In this paper, we first discuss how to characterize and model STI CMP process. Once STI CMP model is developed, it can be used for screening design and detect possible manufacturing weak spots. We also work with process engineering team to establish hotspot criteria in terms of oxide dishing and nitride loss.

As process technologies move from planar transistor to 3D transistor like FinFet and multi-gate, it is important to accurately predict topography in FEOL CMP processes. These incoming topographies when stacked up can have huge impact in BEOL copper processes, where copper pooling becomes catastrophic yield loss. A calibration methodology to characterize STI CMP step is developed as shown in Figure 1; moreover, this STI CMP model is validated from silicon data collected from product chips not used in calibration stage. Additionally, wafer experimental setup and metrology plan are instrumental to an accurate model with high predictive power.

After a model is generated, spec limits and threshold to establish hotspots criteria can be defined. Such definition requires working closely with foundry process engineering and integration team and reviewing past failure analysis (FA) to come up a reasonable metrics. Conventionally, a potential STI weak point can be found when nitride residues remains in the active region after nitride strip. Another source of STI hotspots occurs when nitride erosion is too much, and active region can suffer severe damage.

Proceedings Article | 16 March 2016 Paper

Design space exploration for early identification of yield limiting patterns

Helen Li, Elain Zou, Robben Lee, Sid Hong, Square Liu, JinYan Wang, Chunshan Du, Recco Zhang, Kareem Madkour, Hussein Ali, Danny Hsu, Aliaa Kabeel, Wael ElManhawy, Joe Kwan

Proceedings Volume 9781, 97810W (2016) https://doi.org/10.1117/12.2218540

KEYWORDS: Monte Carlo methods, Optical lithography, Design for manufacturing, Lithography, Resolution enhancement technologies, Design for manufacturability, Manufacturing, Visualization, Legal, Double patterning technology, Acquisition tracking and pointing, Optical proximity correction, Roads

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Proceedings Article | 18 March 2015 Paper

Layout dependent effects analysis on 28nm process

Helen Li, Mealie Zhang, Waisum Wong, Huiyuan Song, Wei Xu, Philippe Hurat, Hua Ding, Yifan Zhang, Michel Cote, Jason Huang, Ya-ch Lai

Proceedings Volume 9427, 94270F (2015) https://doi.org/10.1117/12.2087443

KEYWORDS: Device simulation, Analog electronics, Diffusion, Tolerancing, Manufacturing, Transistors, Semiconductor manufacturing, Roads, Physical phenomena, Design for manufacturability

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