Dr. Xin Wu Profile

Dr. Xin Wu

Engineer at Advanced Micro Devices Inc

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Publications (8)

Proceedings Article | 27 June 2019 Open Access

FPGA capability expansion despite technology challenges

Nui Chong, Xin Wu

Proceedings Volume 11178, 1117802 (2019) https://doi.org/10.1117/12.2537628

KEYWORDS: Field programmable gate arrays, Logic, System on a chip, Analog electronics, Artificial intelligence, Photomasks, Machine learning, Semiconductors

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Proceedings Article | 16 September 2014 Paper

Double-patterning optimization in 20nm SRAM design

Qi Lin, Toshiyuki Hisamura, Nui Chong, Hans Pan, Yun Wu, Jonathan Chang, Xin Wu

Proceedings Volume 9235, 923505 (2014) https://doi.org/10.1117/12.2066262

KEYWORDS: Double patterning technology, Diffusion, Photomasks, Optical proximity correction, Critical dimension metrology, Silicon, Field programmable gate arrays, Semiconducting wafers, Optical lithography, Optical alignment

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Proceedings Article | 23 September 2009 Paper

Fabless company mask technology approach: fabless but not fab-careless

Toshiyuki Hisamura, Xin Wu

Proceedings Volume 7488, 748821 (2009) https://doi.org/10.1117/12.833505

KEYWORDS: Photomasks, Semiconducting wafers, Manufacturing, Field programmable gate arrays, Air contamination, Failure analysis, Mask making, Critical dimension metrology, Resolution enhancement technologies

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There are two different foundry-fabless working models in the aspect of mask. Some foundries have in-house mask facility while others contract with merchant mask vendors. Significant progress has been made in both kinds of situations. Xilinx as one of the pioneers of fabless semiconductor companies has been continually working very closely with both merchant mask vendors and mask facilities of foundries in past many years, contributed well in both technology development and benefited from corporations. Our involvement in manufacturing is driven by the following three elements: The first element is to understand the new fabrication and mask technologies and then find a suitable design / layout style to better utilize these new technologies and avoid potential risks. Because Xilinx has always been involved in early stage of advanced technology nodes, this early understanding and adoption is especially important. The second element is time to market. Reduction in mask and wafer manufacturing cycle-time can ensure faster time to market. The third element is quality. Commitment to quality is our highest priority for our customers. We have enough visibility on any manufacturing issues affecting the device functionality. Good correlation has consistently been observed between FPGA speed uniformity and the poly mask Critical Dimension (CD) uniformity performance. To achieve FPGA speed uniformity requirement, the manufacturing process as well as the mask and wafer CD uniformity has to be monitored. Xilinx works closely with the wafer foundries and mask suppliers to improve productivity and the yield from initial development stage of mask making operations. As an example, defect density reduction is one of the biggest challenges for mask supplier in development stage to meet the yield target satisfying the mask cost and mask turn-around-time (TAT) requirement. Historically, masks were considered to be defect free but at these advanced process nodes, that assumption no longer holds true. There is a need to be flexible enough on unrepairable defect at early stage but also a need for efficient risk management system on mask defect waivers. Mask defects are often waived in low design criticality area in favor of scrapping the mask and delaying the mask and wafer schedule. Xilinx's involvement in mask manufacturing has contributed significantly to our success in past many nodes and will continue.

Proceedings Article | 4 March 2008 Paper

A procedure to back-annotate process induced layout dimension changes into the post layout simulation netlist

Jonathan Ho, Yan Wang, Xin Wu, Jane Soward, Ping Zhang, Joanne Wu

Proceedings Volume 6925, 69250V (2008) https://doi.org/10.1117/12.771427

KEYWORDS: Transistors, Diffusion, Optical proximity correction, Lithography, Semiconducting wafers, Oscillators, Etching, Standards development, Model-based design, Scanning electron microscopy

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As transistor dimensions become smaller, on-wafer transistor dimension variations, induced by lithography or etching process, impact more to the transistor parameters than those from the earlier process technologies such as 90 nm and 130 nm. The on-wafer transistor dimension variations are layout dependent and are ignored in the standard post layout verification flow where the transistor parameters in a spice netlist are extracted from drawn transistor dimensions. There are commercial software tools for predicting the on-wafer transistor dimensions for the improved accuracy of the post-layout verification. These tools need accurate models for the on-wafer transistor dimension prediction and the models need to be re-calibrated as the fabrication process is changed. Furthermore, the model-based predictions of the on-wafer transistor dimensions require extensive computing power which can be time consuming. In the paper, a procedure to back-annotate the process induced transistor dimension changes into the post layout extracted netlist using a simple look-up table is described. The lookup table is composed of specified drawn transistor and its sounding layout as well as their on-wafer dimensions. The on-wafer dimensions can be extracted from simulations, SEM in-line pictures or electrical data of specially designed testkeys. Taking the lookup table data, accordingly, the transistor dimensions in the post-layout netlist file are then modified by a commercial software tool with a pattern search function. Comparing with the model based approach, the lookup table approach takes much less time for modifying the post-layout netlist. The lookup table approach is flexible, since the tables can be easily updated to reflect the most recent process changes from the foundry. In summary, a lookup table based approach for improving the post-layout verification accuracy is described. This approach can improve the verification accuracy from both litho and non-litho process variations. This approach has been applied to Xilinx's 65 nm and 45 nm product developments.

Proceedings Article | 21 March 2006 Paper

Inverse lithography technology at chip scale

Benjamin Lin, Ming Feng Shieh, Jie-wei Sun, Jonathan Ho, Yan Wang, Xin Wu, Wolfgang Leitermann, Orson Lin, Jason Lin, Yong Liu, Linyong Pang

Proceedings Volume 6154, 615414 (2006) https://doi.org/10.1117/12.656827

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Manufacturing, Scanning electron microscopy, Calibration, Image quality, Semiconducting wafers, Image processing, Semiconductors

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Proceedings Article | 9 November 2005 Paper

FPGA chip performance improvement with gate shrink through alternating PSM 90nm process

Chun-Chi Yu, Ming-Feng Shieh, Erick Liu, Benjamin Lin, Jonathan Ho, Xin Wu, Petrisor Panaite, Manoj Chacko, Yunqiang Zhang, Wen-Kang Lei

Proceedings Volume 5992, 59925A (2005) https://doi.org/10.1117/12.637426

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Critical dimension metrology, Design for manufacturing, Halftones, Manufacturing, Semiconducting wafers, Image processing, Field programmable gate arrays

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Proceedings Article | 5 November 2005 Paper

Real-world impacts of inverse lithography technology

Jonathan Ho, Yan Wang, Xin Wu, Wolfgang Leitermann, Benjamin Lin, Ming Feng Shieh, Jie-wei Sun, Orson Lin, Jason Lin, Yong Liu, Linyong Pang

Proceedings Volume 5992, 59921Z (2005) https://doi.org/10.1117/12.632211

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Manufacturing, Scanning electron microscopy, Calibration, Image quality, Semiconducting wafers, Semiconductors, Image segmentation

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Proceedings Article | 5 May 2005 Paper

DFM in practice: results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90-nm FPGA chip

Chun-Chi Yu, Ming-Feng Shieh, Erick Liu, Benjamin Lin, Henry Lin, Manoj Chacko, Xiaoyang Li, Wen-Kang Lei, Jonathan Ho, Xin Wu

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.598838

KEYWORDS: Photomasks, Design for manufacturing, Optical proximity correction, Critical dimension metrology, Image processing, Manufacturing, Electronic design automation, Etching, Halftones, Lithography

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Showing 5 of 8 publications

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