In this paper, current density-voltage (J-V) characteristic of dual trench diode array have been investigated by both TCAD model and experimental method. It is shown that the arsenic concentration in buried N+ layer (BNL), epitaxial (EPI) layer thickness, and the dosage of P region in PN junction are expected to be the prominent factors responsible for both of the leakage and drive current performance according to TCAD simulation. By introducing the optimal siliconbased results, the 4×4 diode arrays were successfully manufactured by 40nm CMOS technology. The median values of drive and reverse leakage current densities are ~7.30×10-2 A/μm2 and 5.61×10-9 A/μm2, respectively. The breakdown voltages (BVDs) of diode array are exceeding 6V, and the Jon/Joff ratios of ~109, which can satisfy the requirements of phase change memory (PCM) applications.
A high density design of Schottky-barrier diode array with self-aligned nickel-silicidation under 40nm technology node fabricated on epitaxial layer for low power phase-change memory application is proposed. According to N-type doping profile from simulation, large ON/OFF current ratio, the lower barrier height of ФB and series resistance RS are all determined by the dosage of buried N+ layer, epitaxial layer thickness. In addition, the temperature effect of the Schottky diode array is demonstrated by I-V electrical characteristics. From the optimal silicon-based results, a 9F2 16 × 16 diode array with the ideality factor of 1.21~1.40 shows a drive current density of ~14.9 mA/μm2, a Jon/Joff ratio of ~5.17×103, and crosstalk immunity. Furthermore, this calibrated physical model makes it possible to predict and improve the performance of accessing device array next generation for non-volatile memory application.
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