This paper proposes dual-mode buffer direct injection (BDI) and direct injection (DI) readout circuit design. The DI readout circuit has the advantage of being a simple circuit, requiring a small layout area, and low power consumption. The internal resistance of the photodetector will affect the photocurrent injection efficiency. We used a buffer amplifier to design the BDI readout circuit since it would reduce the input impedance and raise the injection efficiency. This paper will discuss and analyze the power consumption, injection efficiency, layout area, and circuit noise. The circuit is simulated using a TSMC 0.35 um Mixed Signal 2P4M CMOS 5 V process. The dimension of the pixel area is 30×30 μm. We have designed a 10×8 array for the readout circuit of the interlaced columns. The input current ranges from 1 nA to 10 nA, when the measurement current is 10 pA to 10 nA. The integration time was varied. The circuit output swing was 2 V. The total root mean square noise voltage was 4.84 mV. The signal to noise ratio was 52 dB, and the full chip circuit power consumption was 9.94 mW.
This paper discusses a capacitor transimpedance amplifier (CTIA) designed for an infrared readout circuit. The CTIA has better gain control, high dynamic range, a stability bias point and low impedance. It applies a short-wave detector and small current source because input impedance is very small in an amplifier feedback mechanism. This research on a capacitor transimpedance amplifier (CTIA) is designed for an infrared readout circuit. It is designed, simulated and laid out using the TSMC 0.35um 2P4M CMOS 5V process. The clock rate operates at 3MHz. Layout area is 30umX30um and the array size is 20X16. The simulation current sets 0.01nA~1.3nA. The output swing is 2.8V and power consumption is 10.1 mW according to the measurement results.
This study proposes a solution for an excessive dark current by a sharing capacitor, which avoids output signal
distortion due to integration voltage saturation. Integration capacitance can be changed by adding a switch in the pixel
circuit, which will increase the capacitance by two times the original. This circuit also provides output functions of either
single-band or dual-band by switching to different sensor. This integrated readout circuit design adopts the TSMC
0.35um 2P4M CMOS 5V process, run on a 5V power supply and operated at a 3MHz clock rate. The dual-band pixel
circuit uses an interlace structure, the pixel circuit areas of the two wavelengths are both 30um x 30um. The mid-wave
and long-wave sensor currents are from 1nA to 2nA and 6nA to 8nA, respectively, and output swing is 2.8V.
This paper proposes two kinds of readout integrated circuits for column and row interlaced dual-band infrared
detectors. The experiments were simulated using TSMC 0.35μm Mixed Signal 2P4M CMOS process and operated at
3MHz clock rate. The pixel dimensions for two kinds of readout integrated circuits were also 30×30μm. The mid-wave
and long-wave sense current was set from 1nA to 2nA and 6nA to 8nA, respectively. We designed a 40x16 array for the
columns interlace readout circuit. The output voltage swing was 2.8V. The frame rate was 4.68kFPS. The total power
consumption was less than 17.6mW. We also designed a 20x32 array for the row interlace readout circuit. The output
voltage swing was 2.8V. The frame rate was 2.67kFPS. The total power consumption was less than 11.4mW. The power
consumption increased when the column interlace frame rate reached the row interlace frame rate. The row interlace can
decrease the layout area by sharing the column stage circuit, but the frame rate will drop to half of the single band frame
rate.
This paper discusses about a readout circuit for Dual-Band Quantum Well Infrared Photo-detectors (DBQWIP)
interlaced focal plane array infrared image system. In this research, we will present the study of modified dark-current
cancellation circuit. The sensing photo-current from 1nA to 10nA of long-wave infrared signal, mid-wave infrared
photo-current is about 100pA to 1nA, the dark current is set up to 100nA. The area of unit pixel is 30×30μm2 . The 8×6
focal-plane array is designed by using TSMC 0.35μm 2P4M CMOS process. This work has 3.3V power supply and
readouts data at 2.5MHz clock rate. The simulated output voltage range of LWIR and MWIR photo-current are 0.95v and
0.76v, respectively.
This paper discussed about a readout circuit for Quantum Dot Infrared Photodetector (QDIP) Focal-Plane-Array
(FPA) imaging system. The readout circuit employed a modified regulated cascode circuit to stabilize the bias of QDIP.
The readout circuit consisted of in-pixel dark current cancellation circuit, sensed current integration and in-pixel switch
integration capacitor. The chip worked at 5V power supply and operated at 1MHz clock rate. Output voltage ranging
from 2 volt to 4 volt was generated when the sensing current from 10nA to 100nA, the dark current was set up to 100nA.
The total power consumption was less than 3.3 mW. The dimension of unit pixel was 30×30μm and the integration
capacitance was about 0.24pF. The 8×8 pixels array readout circuit of in-pixel variable integration capacitors was
implemented by using TSMC 0.35μm Mixed Signal 2P4M CMOS process.
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