Side-channel attacks (SCAs) have become one of the main threats to encryption devices due to their low cost, short time, and strong attack capability. CPU is the core of encryption devices. Thus the resistance to SCAs of the CPU is essential for protecting encrypted information. Based on the register-transfer level (RTL) net-list simulation and CPA method, this paper carries out SCAs on the CPU running the AES-128 algorithm. A protection scheme based on random power consumption disturbance strategy is proposed. It uses register configuration to send random pseudo operation insertion requests to some idle modules inside the CPU at a certain frequency, thereby reducing the correlation between the power consumption and encrypted data. This paper innovatively analyses the effects of the number of randomly flipped modules and the insertion frequency of random pseudo operation on the CPU's resistance to SCAs. According to experimental results, when the CPU is not protected, only 30 power traces are able to reveal the correct key. The required trace number increases when the random power consumption disturbance strategy is applied. The anti-attack performance of the CPU is proportional to the number of randomly flipped idle modules, and approximately inversely proportional to the power consumption signal-to-noise ratio (SNR). Particularly, when all idle modules randomly flip at a frequency of 25%, the CPU’s anti-attack performance has been improved by 3700 times. The proposed protection scheme is simple, easy to implement and highly flexible, by taking the safety performance, power consumption, area and other factors into consideration.
KEYWORDS: Failure analysis, Field effect transistors, High power microwaves, Integrated circuits, Electromagnetism, 3D modeling, Scanning electron microscopy, Electrical breakdown, System on a chip
The Electrical Fast Transient (EFT) interference may affect the performance of the device or even cause the device failure. To study the anti-EFT interference performance of integrated circuit (IC), an EFT test platform of a SoC MCU chip has been set up. And the power pin of MCU integrated circuit shows better anti-interference performance than that of interface pin. Since I/O failure is mainly caused by MOSFET failure in clamp circuit, OBIRCH, SEM and other means are used to locate the failure position and accurately analyze the failure points. And the failure mechanism of the MOSFET in the I/O circuit has been analyzed according to the observation results. The MOSFET in the I/O circuit is fused under the positive feedback effect of the decrease of resistivity and the increase of current density, which leads to the I/O failure. The failure mechanism of MOSFET under high speed pulse is also verified by simulation. The results show that the only hot spot, firstly reaching the silicon melting point due to heat deposition originating from Electromagnetic Pulse (EMP) injection, is at the drain-substrate PN junction. The device fails or burns out with thermally damages due to electrical heating coupling.
Based on the principle of SSD (Single Shot Multibox Detector) convolutional neural network algorithm, this paper develops corresponding training strategies, and uses the source data generated under a large number of power-grid scenarios to train and generate a 100-megabyte neural network model for intelligent monitoring of external force damage on transmission lines. Using the deep compression technology, the trained neural network model is re-trained and optimized in a targeted manner to ensure a compression ratio of 30%-50% under the premise that the accuracy is not degraded. In this way, the hardware storage resource configuration is more reasonable when the model is deployed on the embedded platform.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.