Dr. Yiming Gu Profile

Dr. Yiming Gu

Photolithograpy Engineer at Texas Instruments Inc

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Publications (9)

Proceedings Article | 17 March 2008 Paper

32nm design rule evaluation through virtual patterning

Scott Jessen, James Blatchford, Steve Prins, Simon Chang, Yiming Gu, Mark Smith, Dale Legband, Chris Sallee

Proceedings Volume 6925, 692518 (2008) https://doi.org/10.1117/12.772685

KEYWORDS: Optical proximity correction, Semiconducting wafers, SRAF, Lithography, Photomasks, Optical lithography, Lithographic illumination, Image segmentation, Manufacturing, Fiber optic illuminators

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Proceedings Article | 5 April 2007 Paper

Characterization of bending CD errors induced by resist trimming in 65 nm node and beyond

Yiming Gu, James Friedmann, Vladimir Ukraintsev, Gary Zhang, Thomas Wolf, Tom Lii, Ricky Jackson

Proceedings Volume 6518, 651826 (2007) https://doi.org/10.1117/12.714479

KEYWORDS: Critical dimension metrology, Cadmium, Semiconducting wafers, Optical proximity correction, Photoresist processing, Plasma, Silicon, Line edge roughness, Etching, Transistors

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Proceedings Article | 24 March 2006 Paper

Local CD variation in 65nm node with PSM processes STI topography characterization (I)

Yiming Gu, Simon Chang, Gary Zhang, Karen Kirmse, Duncan Rogers, Leif Olsen, John Lewellen

Proceedings Volume 6152, 615204 (2006) https://doi.org/10.1117/12.655914

KEYWORDS: Critical dimension metrology, Transistors, Semiconducting wafers, Cadmium, Optical proximity correction, Etching, Logic, Line edge roughness, Line width roughness, Scanning electron microscopy

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How to effectively control the critical dimension (CD) is always a hot topic in photolithography. In 65nm node using phase shift mask (PSM) techniques, any factors related to CD variations should not be ignored without full investigation due to the ever-decreasing CD budget. In this paper, we focus on the local CD variation (LCDV) at the gate level within an area of 200μm x 200μm printed on a 193nm exposure tool. In contrast with AWLV (across wafer line variation) and ACLV (across chip line variation), the more localized LCDV implies that it is more dependent on the following three major factors: i) local wafer flatness mainly dominated by STI (shallow trench isolation) steps after CMP (chemical mechanical polishing); ii) effectiveness of OPC (optical proximity correction) covering all transistors with different geometrical shapes in circuit layout and iii) line edge roughness (LER) and line width roughness (LWR) related to photo and etch processes. Although OPC errors, LER and LWR are also very important, the current discussion will be limited in characterizing the relationship between LCDV and STI step-height (S-H) due to the length limitation. The STI S-H between the active surface and the trench oxide surface always exists due to the different material selectivity in the CMP process. The major gate CD influences from STI S-H are strongly correlated to the different geometrical shapes of transistors in circuits, such as single/multi-finger, wide/narrow, interior/exterior-flare and etc. According to our experiments and simulations from both alt-PSM (alternating PSM) and att-PSM (attenuating PSM) processes, the following important conclusions can be derived. a) The gate CDs in two PSM processes show different sensitivities to STI S-Hs in different geometrical shapes of transistors in circuit layout. The alt-PSM process is more sensitive than the att-PSM, especially for isolate gates. This is a shortcoming for the alt-PSM process in effectively controlling the LCDV. b) STI S-H usually makes the CD larger in both PSM processes, especially for the isolated gates in the alt-PSM process. From our observations, it is generally true that the narrower the transistor width, the higher the gate CD will be. However, CD variation trends in the att-PSM process are not so explicit as observed with alt-PSM. c) One should be very careful when trying to improve the CD uniformity by reducing STI step-height by using a blanket etch back because OPC errors are tightly combined with STI step-heights. d) Improving the STI S-H uniformity is always welcome because it will improve the AWLV. e) The narrow isolated gate is the best CD feature to monitor the interaction of AWLV with STI S-H uniformity.

Proceedings Article | 24 May 2004 Paper

Dielectric antireflection layer optimization: correlation of simulation and experimental data

Yiming Gu, Anthony Wang, Dyiann Chou

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.536560

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Reflectivity, Metals, Manufacturing, Reticles, Dielectrics, Calibration, Antireflective coatings, Coating

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The continuing shrinkage of device size will result in stringent demands on high precision CD control. For example, at 0.13um technology node a typical poly gate size variation should be controlled within +/- 8nm or even smaller. This tight CD budget includes all possible variations which can be from different modules of resist coating track, optical and mechanical parts of exposure tool, non-uniformity of wafer substrate, CD metrology, mask making and so on. Particularly, the residual swing effect after applying an inorganic anti-reflection layer (SiON) still can claim a significant CD budget if not properly optimized. Therefore, how to minimize the residual swing effect still plays important role in CD control. Simulation of reflectivity is considered analytically rigorous and is therefore frequently employed to aid in process development. However, since in manufacturing environments people usually pay more attention to the repeatability of optical metrology tools rather than their accuracies, it is not surprising if some significant discrepancies exist between theoretical and experimental results. Instead of discussing the detail error sources and the tool calibrations, a quick and convenient experimental methodology is introduced to account for such differences and to optimize the film stack composition effectively. In this paper, with the CD variations on metal and poly substrates as examples, an effective combination between the calculations and the experiments is presented in order to minimize the CD swing. We also demonstrate that with the "single wafer swing curve" technique, the residual swing effect can be easily detected and minimized. This methodology provides a possibility to determine the best anti-reflection layer not only from theoretical but also from experimental point of view in manufacturing environments. Since the residual swing effect is a common issue, the results of this paper can be widely used in either manufacturing fabs or experimental labs.

Proceedings Article | 12 June 2003 Paper

Reduction of implantation shadowing effect by dual-wavelength exposure photo process

Yiming Gu, Dyiann Chou, Sang Yun Lee, William Roche, John Sturtevant

Proceedings Volume 5039, (2003) https://doi.org/10.1117/12.485103

KEYWORDS: Deep ultraviolet, Photoresist processing, Semiconducting wafers, Manufacturing, Silicon, Tolerancing, Optical lithography, Ions, Absorption, Ion implantation

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Proceedings Article | 2 June 2003 Paper

Single wafer process to generate reliable swing curves

Yiming Gu, Cynthia Zhu, John Sturtevant

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483435

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Silicon, Coating, Silicon films, Reflectivity, Photoresist processing, Photoresist materials, Signal to noise ratio, Solids

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Swing curve generation is an important and common exercise in the design, characterization, and optimization of photolithography processes. The development of a robust anti-reflective strategy for a given process often necessitates multiple experimental iterations of the swing curve generation. The traditional methodology for generating a photoresist thickness swing curve plot is time and silicon intensive; usually involving processing and metrology on a dozen or more wafers. In addition, the resulting curve often can convolve systematic and random wafer-wafer effects due to other track/resist/scanner related variables. In some cases, such as very low reflectivity underlying substrate the signal to noise ratio is poor enough to effectively mask the sinusoidal swing behavior from visibility. In this paper, we present a new methodology to generate a swing curve by using a single wafer. The critical point of this method is to generate a temperature gradient on the wafer during the initial step of photoresist dispense and coating. Since the resist viscosity is inversely proportional to the temperature, a significant resist thickness variation can be produced across the wafer, which can easily encompass one swing period of thickness or more. The resulting resist thickness signature across the wafer is seen to be very repeatable, such that a companion wafer can be measured at multiple positions corresponding to CD metrology lcoations on the patterned wafer. The possibility of deconvolving systematic across wafer CD variability due to other process variables is discussed by characterizing a control wafer with conventional uniform resist thickness. Our experiments for I-line and DUV resists indicated that this method not only provides reliable swing curves but also saves photoresist, silicon, and time both for engineering and machine. Moreover, this methodology represents an improved signal to noise ratio such that makes it particularly useful for ARC thickness/composition optimization. Several examples utilizing this method will be presented.

Proceedings Article | 2 June 2003 Paper

Resist compacting under SEM E-Beam

Yiming Gu, Dyiann Chou, John Sturtevant

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483432

KEYWORDS: Scanning electron microscopy, Critical dimension metrology, Deep ultraviolet, Image quality, Cadmium, Optical testing, Polymers, Etching, Optics manufacturing, UV optics

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Proceedings Article | 30 July 2002 Paper

Reduction of reflective notching through illumination optimization

James Word, Dyiann Chou, Yiming Gu, John Sturtevant

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474566

KEYWORDS: Reflectivity, Photoresist materials, Scanning electron microscopy, Distortion, Semiconducting wafers, Photography, Optical lithography, Bottom antireflective coatings, Photomasks, Critical dimension metrology

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Proceedings Article | 16 July 2002 Paper

Characterization and reduction of highly localized substrate contamination defects in metal patterning

Yiming Gu, Anqing Zhang, Zhenjiang Yu, Wanqing Cao, Sean Chen, John Sturtevant, Shih-Ked Lee

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473504

KEYWORDS: Contamination, Metals, Tin, Photoresist processing, Etching, Coating, Optical lithography, Semiconducting wafers, Resistance, Scanning electron microscopy

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The reduced CD (critical dimension) of devices places more stringent requirements on the photo process for metal layers, especially for the metal local-interconnect (MLIC) or M0 layer, which can have a minimum dimension similar to poly-gate. This layer has shown a highly localized substrate contamination defect with chemically-amplified (CA) DUV photoresists, which is related to the underlying contact plug. The failure analysis shows that reducing this defect plays an import role in enhancing the yield of a SRAM used as a test vehicle in process development. After transistors are formed, contacts to gates and source/drain regions are opened and subsequently filled with W-plugs, then a PVD TiN film is deposited as a MLIC layer between transistors. A silicon oxynitride (SiON) film is deposited as an anti-reflection layer, and a SiO2 cap is utilized as a substrate contamination barrier. However, with such a film structure, after resist patterning etch and cleaning, one major defect was often observed at the final inspection stage. This defect was always spatially-correlated to an underlying contact plug, and resulted in highly localized 'swelling' or bridging of adjacent photoresist features. In this paper, the MLIC swelling defect is characterized and its possible root causes are discussed. The correlation between the defect and the type of resist (high activation energy and low activation energy) is investigated as well. In order to eliminate the defect thoroughly or to reduce the number of defects substantially, many experimental tests have been carried out, which include the defectivity comparisons with different resists, the application of an organic bottom anti-reflection coating (BARC), the outgas reduction for poly-metal dielectric (PMD) layers, the optimization of resist striping procedure for implant layer before metal deposition, the double CA resist coating and so on. The results indicate that it is possible to eliminate the swelling defect at the photo stage by applying several special treatments.

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