With increasing chip sizes and shrinking device dimensions, on-chip semiconductor process variation can no longer be ignored in the design and signoff static timing analysis of integrated circuits. An important parameter affecting CMOS technologies is the gate length (Lgate) of a transistor. In modern technologies significant spatial intra-chip variability of transistor gate lengths which are systematic, as opposed to random, can lead to relatively large variations in circuit path delays. Spatial variations in Lgate affect circuit timing properties, which can lead to timing errors and performance loss. To maximize performance and process utilization in microprocessor designs, we have developed and validated a timing analysis methodology based on accurate silicon contour prediction from drawn layout and contour-based extraction of our designs. This allows for signoff timing without unnecessarily large margins, thereby reducing chip area and maximizing performance while ensuring chip functionality, improved process utilization and yield. In this paper we describe such a chip timing methodology, its validation and implementation in microprocessor design. We also report results of layout optimization based on new pattern matching technology.
An AC current induced electromigration (EM) on clock and logic signals becomes a significant problem even in the presence of reverse-recovery effect. Compared to power network, clock and logic signal interconnects are much narrower (mostly drawn up to the minimum width and space) and suffer from fast switching and large driving current from FinFETs. Thus, the high current density on those signal interconnects can cause a serious failure. In this paper, we analyse EM on signal interconnects in 16nm FinFET design, and characterize the impact of process variations, e.g., lithography and etch process, CMP (chemical-mechanical polishing) process, redundant via, etc. Then we optimize the signal lines with various design approaches to mitigate EM problem in 16nm design.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.