In advanced DRAM semiconductor manufacturing, there is a need to reduce the overlay fingerprints. Reducing on device fingerprints with very high spatial frequency remains one of the bottlenecks to achieve sub-2nm on device overlay. After-etch device overlay measurements using the YieldStar in-device metrology (IDM)[1] allow for previously unassessed and uncontrolled fingerprints to be corrected employing higher-order overlay corrections. This is because this technology allows dramatically increased overlay metrology sampling at affordable throughputs. This paper reports considerations for enabling dense after-etch overlay based corrections in a high volume manufacturing environment. Results will be shown on a front end critical layer of SK hynix that has been sampled with IDM with high density wafer sampling, over dozens of lots spanning several weeks.
With shrinking design rules, the overall patterning requirements are getting aggressively tighter and tighter, driving requirements for on-product overlay performance below 2.5nm and CD uniformity requirements below 0.8nm. Achieving such performance levels will not only need performance optimization of individual tools but a holistic optimization of all process steps. This paper reports on the first step towards holistic optimization – co-optimized performance control of scanner and etch tools. In this paper we evaluate the use of scanner and etcher control parameters for improvement of after final etch overlay and CD performance. The co-optimization of lithography and etch identifies origins of the variabilities and assigns corrections to corresponding tools, handles litho-etch interactions and maximizes the correction capability by utilizing control interfaces of both scanner and etch tools in a single control loop. The product aims to improve total variability measured after etch as well as fingerprint matching between tools. For CD control we co-optimize the dose corrections on the lithography tool with the temperature corrections on the etcher. This control solution aims to correct CD variabilities originating at deposition, lithography and etcher. For overlay we co-optimize the overlay inter and intra-field grid interfaces on the scanner with the wafer edge ring height compensation on the etcher. The evaluation of both CD and overlay control solutions is performed for the 2xnm DRAM node of SK hynix DRAM group. YieldStar in-device metrology after core etch was used for CD control. On wafer verification showed an improvement of 23% of the total CD variation. In-device metrology after final etch was user for overlay control. Evaluation showed 35% improvement in total overlay variability due to scanner-etch co-optimization.
To support the manufacturing of DRAM semiconductors for next and future nodes, there is a constant need to reduce the overlay fingerprints. In this paper we evaluate algorithms which are capable of decoupling wafer deformation from mark deformation and extrapolation effects. The algorithms enable lithography tools to use only the wafer deformation component in the alignment feedforward correction. Therefore improving the (wafer to wafer) overlay. First results will be shared showing improvement of wafer to wafer variation in high-volume manufacturing environment.
This paper demonstrates the improvement using the YieldStar S-1250D small spot, high-NA, after-etch overlay in-device measurements in a DRAM HVM environment. It will be demonstrated that In-device metrology (IDM) captures after-etch device fingerprints more accurately compared to the industry-standard CDSEM. Also, IDM measurements (acquiring both CD and overlay) can be executed significantly faster increasing the wafer sampling density that is possible within a realistic metrology budget. The improvements to both speed and accuracy open the possibility of extended modeling and correction capabilities for control. The proof-book data of this paper shows a 36% improvement of device overlay after switching to control in a DRAM HVM environment using indevice metrology.
As semiconductor manufacturing technology progresses and the dimensions of integrated circuit elements shrink, overlay budget is accordingly being reduced. Overlay budget closely approaches the scale of measurement inaccuracies due to both optical imperfections of the measurement system and the interaction of light with geometrical asymmetries of the measured targets. Measurement inaccuracies can no longer be ignored due to their significant effect on the resulting device yield. In this paper we investigate a new approach for imaging based overlay (IBO) measurements by optimizing accuracy rather than contrast precision, including its effect over the total target performance, using wavelength tunable overlay imaging metrology. We present new accuracy metrics based on theoretical development and present their quality in identifying the measurement accuracy when compared to CD-SEM overlay measurements. The paper presents the theoretical considerations and simulation work, as well as measurement data, for which tunability combined with the new accuracy metrics is shown to improve accuracy performance.
Hyun-Sok Kim, Min-Sung Hyun, Jae-Wuk Ju, Young-Sik Kim, Cees Lambregts, Peter van Rhee, Johan Kim, Elliott McNamara, Wim Tel, Paul Böcker, Nang-Lyeom Oh, Jun-Hyung Lee
Computational metrology has been proposed as the way forward to resolve the need for increased metrology density, resulting from extending correction capabilities, without adding actual metrology budget. By exploiting TWINSCAN based metrology information, dense overlay fingerprints for every wafer can be computed. This extended metrology dataset enables new use cases, such as monitoring and control based on fingerprints for every wafer of the lot. This paper gives a detailed description, discusses the accuracy of the fingerprints computed, and will show results obtained in a DRAM HVM manufacturing environment. Also an outlook for improvements and extensions will be shared.
In recent years, lithographic printability of overlay metrology targets for memory applications has emerged as a significant issue. Lithographic illumination conditions such as extreme dipole, required to achieve the tightest possible pitches in DRAM pose a significant process window challenge to the metrology target design. Furthermore, the design is also required to track scanner aberration induced pattern placement errors of the device structure. Previous workiii, has shown that the above requirements have driven a design optimization methodology which needs to be tailored for every lithographic and integration scheme, in particular self-aligned double and quadruple patterning methods. In this publication we will report on the results of a new target design technique and show some example target structures which, while achieving the requirements specified above, address a further critical design criterion – that of process resilience.
We present a metrology target design (MTD) framework based on co-optimizing lithography and metrology performance. The overlay metrology performance is strongly related to the target design and optimizing the target under different process variations in a high NA optical lithography tool and measurement conditions in a metrology tool becomes critical for sub-20nm nodes. The lithography performance can be quantified by device matching and printability metrics, while accuracy and precision metrics are used to quantify the metrology performance. Based on using these metrics, we demonstrate how the optimized target can improve target printability while maintaining the good metrology performance for rotated dipole illumination used for printing a sub-100nm diagonal feature in a memory active layer. The remaining challenges and the existing tradeoff between metrology and lithography performance are explored with the metrology target designer’s perspective. The proposed target design framework is completely general and can be used to optimize targets for different lithography conditions. The results from our analysis are both physically sensible and in good agreement with experimental results.
Advancing technology nodes with smaller process margins require improved photolithography overlay control. Overlay control at develop inspection (DI) based on optical metrology targets is well established in semiconductor manufacturing. Advances in target design and metrology technology have enabled significant improvements in overlay precision and accuracy. One approach to represent in-die on-device as-etched overlay is to measure at final inspection (FI) with a scanning electron microscope (SEM). Disadvantages to this approach include inability to rework, limited layer coverage due to lack of transparency, and higher cost of ownership (CoO). A hybrid approach is investigated in this report whereby infrequent DI/FI bias is characterized and the results are used to compensate the frequent DI overlay results. The bias characterization is done on an infrequent basis, either based on time or triggered from change points. On a per-device and per-layer basis, the optical target overlay at DI is compared with SEM on-device overlay at FI. The bias characterization results are validated and tracked for use in compensating the DI APC controller. Results of the DI/FI bias characterization and sources of variation are presented, as well as the impact on the DI correctables feeding the APC system. Implementation details in a high volume manufacturing (HVM) wafer fab will be reviewed. Finally future directions of the investigation will be discussed.
Extreme Ultraviolet (EUV) is the most promising technology as substitute for multiple patterning based on ArF immersion lithography. If enough productivity can be accomplished, EUV will take main role in the chip manufacturing. Since the introduction of NXE3300, many significant results have been achieved in source power and availability, but lots of improvements are still required in various aspects for the implementation of EUV lithography on high volume manufacturing. Among them, it is especially important to attain high sensitivity resist without degrading other resolution performance. In this paper, performances of various resists were evaluated with real device patterns on NXE3300 scanner and technical progress of up-to-date EUV resists will be shown by comparing with the performance of their predecessors. Finally the prospect of overcoming the triangular trade-off between sensitivity, resolution, line edge roughness (LER) and achieving high volume manufacturing will be discussed.
Spacer multi patterning process continues to be a key enabler of future design shrinks in DRAM and NAND process flows. Improving Critical Dimension Uniformity (CDU) for main features remains high priority for multi patterning technology and requires improved metrology and control solutions.
In this paper Spacer Patterning Technology is evaluated using an angle resolved scatterometry tool for both intra field control of the core CD after partition etch (S1) and interfield pitch-walking control after final etch (S1-S2). The intrafield measurements were done directly on device using dense sampling. The inter-field corrections were based on sparse full wafer measurements on biased OCD targets. The CDU improvement after partition-etch was verified by direct scatterometer and CD-SEM measurement on device. The final etch performance across wafer was verified with scatterometer on OCD target.
The scatterometer metrology in combination with the control strategy demonstrated a consistent CDU improvement of core (S1) intrafield CD after partition etch between 23-39% and 47-53% on interfield pitch-walking (S1-S2) after final etch. To confirm these improvements with CD-SEM, oversampling of more than 16 times is needed compared to scatterometer.
Based on the results it is concluded that scatterometry in combination with the evaluated metrology and control strategy in principle qualifies for a spacer process CDU control loop in a manufacturing environment.
As DRAM semiconductor manufacturing approaches high volume for 1x nm nodes with immersion lithography, an increased emphasis is being placed on reducing the influence of the systematic wafer-level contribution to the on-product overlay budget. The cost of the needed metrology has hitherto been challenging. However, it will be shown that the availability of fast, accurate diffraction based metrology integrated within the Lithography cluster can enable cost-effective solutions. Together with applications software we will use any relevant context information to optimize control of all exposure-tool actuators during lot processing, to deliver the needed on-product performance.
Current process corrections typically are done based on feedback per lot and per exposure chuck. Wafers exposed on the same chuck, belonging to the same lot get exactly the same process corrections. In current HVM processing however, an important contribution to the wafer variation is the differences in processing of the individual wafers. These differences can be related to variations in the usage of the processing tools (e.g. different etch chambers). An extension of the process corrections from chuck-based to process-context based can help in reducing the systematic wafer-level variation. With Integrated Metrology the sampling of wafers through the lot can be adjusted to make sure all different processing-contexts are covered in the measurements.
Finally, the impact on Litho process cycle time of the total metrology effort required to enable these performance improvements, will be evaluated, and a proposal will be made on the optimum strategy to enable high-volume manufacturing.
Stochastic noise has strong impact on local variability such as LWR (Line Width Roughness), LCDU (Local Critical Dimension Uniformity) and LPE (Local Placement Error), and it is basically originated from the particle nature of photon. Statistical uncertainties of particles, same as the stochastic noises, can be analytically calculated by considering aerial image as a probability density function of photons. Contact-hole is the best pattern for counting its photon, so LCDU of contact-hole array is estimated and compared with experimental results. Among several possible statistical events from mask to resist pattern, three independent events of aerial image formation, photon absorption in resist, and chemical reaction including acid generation are considered to predict stochastic noise for both EUV (Extreme Ultra Violet) and ArF immersion lithography.
As EUV reaches high volume manufacturing, scanner source power and reticle defectivity attract a lot of attention. Keeping a EUV mask clean after mask production is as essential as producing a clean EUV mask. Even though EUV pellicle is actively investigated, we might expose EUV masks without EUV pellicle for some time. To keep clean EUV mask under pellicle-less lithography, EUV scanner cleanliness needs to meet the requirement of high volume manufacturing. In this paper, we will show the cleanliness of EUV scanners in view of mask particle adders during scanner exposure. From this we will find several tendencies of mask particle adders depending on mask environment in scanner. Further we can categorize mask particle adders, which could show the possible causes of particle adders during exposure in scanners.
In order to handle the upcoming 1x DRAM overlay and yield requirements, metrology needs to evolve to more accurately represent product device patterns while being robust to process effects. One way to address this is to optimize the metrology target design. A viable solution needs to address multiple challenges. The target needs to be resistant to process damage. A single target needs to measure overlay between two or more layers. Targets need to meet design rule and depth of focus requirements under extreme illumination conditions. These must be achieved while maintaining good precision and throughput with an ultra-small target. In this publication, a holistic approach is used to address these challenges, using computationally optimized metrology targets with an advanced overlay control loop.
In this paper we describe the joint development and optimization of the critical dimension uniformity (CDU) at an advanced 300 mm ArFi semiconductor facility of SK Hynix in the high volume device. As the ITRS CDU specification shrinks, semiconductor companies still need to maintain high wafer yield and high performance (hence market value) even during the introduction phase of a new product. This cannot be achieved without continuous improvement of the on-product CDU as one of the main drivers for yield improvement. ASML Imaging Optimizer is one of the most efficient tools to reach this goal. This paper presents experimental results of post-etch CDU improvement by ASML imaging optimizer for immature photolithography and etch processes on critical features of 20nm node. We will show that CDU improvement potential and measured CDU strongly depend on CD fingerprint stability through wafers, lots and time. However, significant CDU optimization can still be achieved, even for variable CD fingerprints. In this paper we will review point-to-point correlation of CD fingerprints as one of the main indicators for CDU improvement potential. We will demonstrate the value of this indicator by comparing CD correlation between wafers used for Imaging Optimizer dose recipe development, predicted and measured CDU for wafers and lots exposed with various delays ranging from a few days to a month. This approach to CDU optimization helps to achieve higher yield earlier in the new product introduction cycle, enables faster technology ramps and thereby improves product time to market.
Small contact holes are the most difficult structures for microlithography to print because it is sensitively affected by the process condition, pattern density and environment as well. Moreover, the patterning of very small contact hole features for the 60nm node DRAM device generation will be a difficult challenge for 248nm lithography. However, we have already demonstrated the applicability of thermal flow resist to print 80nm contact holes for DRAM device using 248nm lithography in previous studies. In this work, we study the potential for contact photoresist reflow to be used with 248nm photoresist to increase process windows of small contact dimensions at the 60nm node DRAM device generation (0.21 k1). With KrF 0.80NA scanner, resist flow process and layout optimization were carried out to achieve the contact hole patterning. And also the exposure condition was optimized. For a contact hole with CDs of 69nm +/- 10%, Focus-Exposure windows over the wafer are 0.25μm and 8%, respectively. In conclusion, we have successfully achieved the contact hole patterning with KrF resist flow process for the 60nm node DRAM device.
One of the crucial tasks of semiconductor process is reduction of manufacturing cost by shrinking the design rule with the help of fine patterning technologies. For high density DRAM application, we explored 0.29 k1 lithography with KrF 0.80NA scanner. Well-known lithography technologies such as asymmetric crosspole, dipole illumination and 6% attenuated PSMs were used for this experiment. Illumination source and mask layout optimization were carried out iteratively to meet CD target, and high contrast thin resist was applied to improve pattern fidelity. Some of the biggest challenges were coping with large MEEF and reducing simulation error. Abnormal non-open fail, probably due to large MEEF, was observed at a dense contact hole pattern. To cope with non-open fail, we tested multi-PSM which composed of alternating PSM along the x-axis direction and 6% attenuated PSM along the y-axis direction. Also we pushed sigma offset of illumination pupil more strongly than exposure tool's specification and there was no serious drawbacks of partial coherency extension. Accurate partial coherence measurement was important for obtaining target CDs and reducing OPC error. For some layers, unexpected simulation error was occurred especially at the patterns of peripheral circuit, therefore we had to calibrate simulation parameters of in-house tool and commercial tool (Solid-C) for OPC simulation. Finally we successfully demonstrated 0.29k1 KrF lithography by showing process yield over 58% in 512Mb DRAM having design rule of 90nm. Based on the results we obtained, we can conclude that 0.29k1 lithography is quite feasible for mass production and 60nm design rule DRAM devices can be manufactured with ArF dry 0.93NA. Since dry 0.93NA corresponds to 1.33NA in ArF water immersion with respect to k1, we can expect that it is possible to fabricate 42nm DRAM devices with ArF immersion lithography.
The Most chip makers want KrF lithography is extended below sub 90nm lithography due to cost and process stability, even though ArF lithography has been growing and its performance is enough to apply to 90nm node. But process control of KrF lithography will become difficult at sub 90nm node because of patterning limitation of KrF lithography. Specially, mask error factor (MEF) is growing to be important for patterning. Generally, chromeless phase shifting mask (PSM) has known widely as a good solution for better patterning than any other PSM, but there are a few companies to apply this mask to their process due to some fatal weakness which are design complexity, difficulties of mask making, control of mask defect, and so on. This paper shows the new modified chromeless HTPSM has solution for some special pattern by using KrF lithography and compares with strong aperture result at 90nm node. The most of island pattern has different MEF with width and length. And patterning control of length axis has been very difficult from mask making to wafer printing. In addition, its control is seriously depended on width axis in the low k1 level. Patterning of storage node contact which is 1:2 duty with width and length axis is very difficult in general DRAM pattern, its MEF is over 5 at width axis and over 15 at length axis in 90nm node. Both axis controls are too hard to achieve good patterning simultaneously. Generally, chromeless PSM has a good MEF performance so we apply and create new modified chromeless HTPSM to overcome our storage node contact pattern. This PSM consist of three layers which are 0° Qz, 180° Qz, and 360° half-tone pattern. 180° Qz pattern play important role in this PSM as a assist pattern to achieve good patterning. First of all, we should make a choice of optimum layout and then we decide on how to make a mask because it is very important factor to control overlay accuracy between 0° Qz and 180° Qz pattern. This overlay accuracy affect to patterning result seriously. Modified chromeless HTPSM has strong patterning performance but overlay accuracy between major and assist pattern will be controlled tightly. This reason is what we hesitate to apply modified chromeless HTPSM to real device development.
95nm KrF lithography has been developed for 512 Mb DRAM. KrF 0.80NA scanner was used to print 190nm pitch patterns and this means the process factor k1 is 0.306. Crosspole illumination was used to print critical layers, which has four poles on x and y-axis. To improve CD uniformity of critical layers we also used fogging effect corrected (FEC) reticles and thin photo resist process, which needs the hard mask etching process to overcome poor dry etch resistance. For 95nm DRAM cell patterns, we could get more than 8% exposure latitude (EL) and 0.3 μm depth of focus (DOF). With FEC masks and optimized resist process, CD uniformity of word line layer printed on wafer was less than 10nm. Overlay accuracy of critical layers is mostly less than 25nm. However at core and periphery area of DRAM the extreme off-axis illumination like crosspole brought poor process latitude in weak zone duties and therefore the hard optical proximity correction (OPC) work was required. In a real integration other novel technologies are used such as gap-filling for STI and ILD processes, Wsi gate, W bit line and SAC processes. This paper reported only lithographic performance for printing 95nm DRAM patterns. Consequently KrF lithography is still promising technology to print sub 100nm node DRAM.
Most chip makers want KrF lithography is extended below sub 100nm lithography due to cost and process stability, even though ArF lithography has been growing and its performance is enough to apply to 100nm node. But process control of KrF lithography will become difficult at sub 100nm node era because of difficulty of mask making, accuracy of optical proximity correction (OPC), lens effects caused by strong off-axis illumination, need more tool accuracies than ever, and so on.
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