Dr. Ana-Maria Armeanu Profile

Dr. Ana-Maria Armeanu

Technical Marketing Engineer at Siemens EDA

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Publications (13)

Proceedings Article | 18 September 2024 Paper

High-NA EUV single patterning of advanced metal logic nodes: inverse lithography techniques in combination with alternative mask absorbers

Ana-Maria Armeanu, Nick Pellens, Vicky Philipsen, Evgeny Malankin, Dongbo Xu, Keisuke Mizuuchi, Gabriel Curvacho, Chih-I Wei, Neal Lafferty, Germain Fenger

Proceedings Volume 13273, 132731M (2024) https://doi.org/10.1117/12.3031718

KEYWORDS: Source mask optimization, Metals, Printing, Nanoimprint lithography, Logic, Lithography, Extreme ultraviolet lithography, 3D mask effects, Extreme ultraviolet, Scanners

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The standard tantalum mask gives strong 3D electromagnetic effects, hence, its utilization in foundries to enable further downscaling to the A14 node might reach its limits even with the help of high NA EUV scanners (with 0.55 numerical aperture “NA”). The use of alternative mask absorber materials together with inverse lithography techniques (ILT), such as source mask optimization (SMO), can improve printing of metal logic layers with a target pitch of 20 and 24nm. This is possible due to thinner mask absorber thickness (around 40nm instead of 60nm for Ta-based mask) and due to different EUV optical properties of the mask material causing a different behavior of the light that is reflected by the masks. To better mitigate the light behavior during and after reflection from the mask, materials covering a good portion of the n-k graph (EUV refractive index, n, by EUV extinction coefficient, k) were chosen. The study proposes a comparison between baseline (Ta-based mask) and five new mask absorber candidates, ranging from three materials with lower refractive index and varied extinction coefficient (“low-n” with low-, mid-, and high-k), and two candidates with higher extinction coefficients (“highk” with mid- and high-n).
This paper contains simulation results with the Siemens EDA Calibre tool and demonstrates theoretical proof that alternative mask materials bring significant gain when compared to the tantalum-based mask absorber. Firstly, we optimized the source and aerial image intensity threshold on a set of predefined clips (with SMO techniques). Secondly, we applied ILT techniques to correct for the full chip mask based on a horizontal layout of a metal logic layer on imec’s roadmap. We then compare the tantalum-based mask with the alternative masks using imaging criteria, such as DoF (depth of focus), NILS (Normalized Image log slope), EPE (edge placement error), pattern shifts through focus, process variation band, source telecentricity errors, and MEEF (mask error enhancement factor) on a variety of features in the metal logic clip to maximize the overall process window.

Proceedings Article | 28 April 2023 Presentation + Paper

Application of resolution enhancement techniques at high NA EUV for next generation DRAM patterning

Ana-Maria Armeanu, Evgeny Malankin, Neal Lafferty, Chih-I Wei, Monica Kempsell Sears, Germain Fenger, Xima Zhang, Werner Gillijns, Darko Trivkovic, Ryoung-han Kim, Jeonghoon Lee

Proceedings Volume 12495, 124950A (2023) https://doi.org/10.1117/12.2660413

KEYWORDS: Photomasks, Extreme ultraviolet, Source mask optimization, Resolution enhancement technologies, Optical proximity correction, Lithography, Optical lithography, Capacitors, Semiconducting wafers, SRAF

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Among several critical layers of DRAM (dynamic random-access memory), capacitor holes of honeycomb arrays and bit-line-periphery (BLP) with Storage Node Landing Pad (SNLP) are the most critical layers in terms of patterning difficulty level. The honeycomb array hole layer has the highest density among various hole array types, and it is a complex lithography step since this layer is key in determining the performance of the DRAM. BLP with SNLP includes hole type and bi-directional line/space (L/S) design, and industry is considering a single exposure solution, compared to a three-mask solution using ArF immersion [1]. This BLP layer of 10nm DRAM has 2 different types of pattern topologies, hole array and bi-direction line/space: it is a very challenging single exposure level. In this paper, we discuss patterning challenges that come as consequences of industry trends in DRAM cell size reduction [2,3]. To keep up with this trend and to propose a single mask solution for bit-line-periphery, storage node landing pads and aggressive cell array pitches are considered along with resolution enhancement techniques (RET) for high-NA anamorphic EUV (NA=0.55) lithography. This study uses computational lithography such as source mask optimization (SMO) to find optimal off-axis illumination and optimal placement of sub-resolution assist features (SRAF) on the mask whilst considering the manufacturing rules checks (MRC constraints) for anamorphic EUV masks. In order to achieve that, a screening Design Technology Co-optimization (DTCO) experiment is done. The purpose is to identify cell array pitches in between 24nm and 32nm which satisfy both scaling requirements and patterning fidelity, preferred orientation of layout, and mask biasing scheme for various cell arrays. Lithography metrics like common depth of focus (cDoF), exposure latitude (EL), image contrast, and image log slope (ILS) are used to decide what is optimal way to expose on wafer. For the sake of completeness of the study, mask materials are compared. Indeed, in EUV domain there is interest to use alternative mask absorbers like Ruthenium alloys as an alternative to Tantalum-based absorbers [4,5,6].

Proceedings Article | 28 April 2023 Paper

Patterning assessment using 0.33NA EUV single mask for next generation DRAM manufacturing

Jeonghoon Lee, Sandip Halder, Van Tuong Pham, Roberto Fallica, Seonggil Heo, Kaushik Sah, Hyo Seon Suh, Victor Blanco, Werner Gillijns, Andrew Cross, Ethan Maguire, Ana-Maria Armeanu, Vladislav Liubich, Evgeny Malankin, Xima Zhang, Monica Kempsell Sears, Neal Lafferty, Germain Fenger, Chih-I Wei, Ryoung Han Kim

Proceedings Volume 12495, 124950S (2023) https://doi.org/10.1117/12.2660763

KEYWORDS: Optical lithography, Extreme ultraviolet, Optical proximity correction, Design and modelling, SRAF, Semiconducting wafers, Inspection, Source mask optimization, Printing, Electronic design automation

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Proceedings Article | 1 December 2022 Poster + Paper

Single mask solution to pattern BLP and SNLP using 0.33NA EUV for next-generation DRAM manufacturing

Kaushik Sah, Andrew Cross, Sayantan Das, Roberto Fallica, Jeonghoon Lee, Ryoung-Han Kim, Sandip Halder, Ethan Maguire, Ana-Maria Armeanu, Monica Sears, Neal Lafferty, Vlad Liubich, Chih-i Wei, Germain Fenger

Proceedings Volume 12292, 122920W (2022) https://doi.org/10.1117/12.2645953

KEYWORDS: Photomasks, Optical proximity correction, Stochastic processes, Extreme ultraviolet, Semiconducting wafers, Wafer-level optics, Source mask optimization, Manufacturing, Inspection, Signal to noise ratio, Defect inspection

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Proceedings Article | 26 September 2019 Paper

Exploring alternative EUV mask absorber for iN5 self-aligned block and contact layers

Rajiv Sejpal, Vicky Philipsen, Ana Armeanu, Chih-I Wei, Werner Gillijns, Neal Lafferty, Germain Fenger, Eric Hendrickx

Proceedings Volume 11148, 111481B (2019) https://doi.org/10.1117/12.2536892

KEYWORDS: Photomasks, Extreme ultraviolet, Extreme ultraviolet lithography, Lithography, Source mask optimization, Nanoimprint lithography, SRAF, Optical proximity correction, Phase shifting, Logic

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Proceedings Article | 2 January 2019 Presentation + Paper

Enabling enhanced EUV lithographic performance using advanced SMO, OPC, and RET

Ana Armeanu, Vicky Philipsen, Fan Jiang, Germain Fenger, Neal Lafferty, Werner Gillijns, Eric Hendrickx, John Sturtevant

Proceedings Volume 10809, 108090G (2019) https://doi.org/10.1117/12.2502809

KEYWORDS: Photomasks, Extreme ultraviolet, Source mask optimization, Resolution enhancement technologies, Tantalum, SRAF, Lithography, Logic, Image enhancement, Image processing

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The current industry standard tantalum-based mask absorber (60 nm TaBN) gives strong 3D electromagnetic field (EMF) effects at wafer level, such as shadowing and pitch-dependent best focus shifts. A thinner mask absorber with higher EUV extinction coefficient or a phase shifting mask can mitigate 3D EMF effects [1]. The alternative mask absorber materials would enable further downscaling to foundry 5nm node using state-of-the-art EUV scanners (with 0.33 numerical aperture “NA”) and facilitate future high NA imaging using single exposure. Here we evaluate insertion options on the patterning roadmap for alternative EUV mask absorbers, including high-k absorbers and attenuated phase shifting masks (attPSM) [1-2]. All studies are using relevant designs from foundry N5 logic node. Two alternative mask candidates are compared with the standard TaBN mask. We bring theoretical proof of concept that alternative mask absorber materials generate significant imaging gain in terms of established success criteria. On a set of predefined types of clips (with variations of 1D/2D, horizontal/vertical, dense/isolated patterns), we seek for higher depth of focus (DoF), higher image log slope (ILS), high illumination efficiency (ideally it would be equal to 1), lower pattern shift through focus (i.e., lower tele-centricity errors), lower mask error enhancement factor (MEEF). Source mask optimization (SMO) on N5 logic clip shows a more balanced source and larger common process window for high-k absorber over Ta-based absorber. Using the optical proximity correction (OPC) engine with high-k mask absorber, shows significant gain on overlapping process window (PW), process variation (PV) band, and less line end shortening. Applying advanced Resolution Enhancement Techniques (RET), sub-resolution assist features (SRAFs) on N5 designs demonstrated an improved process in terms of common depth of focus (cDoF), and image shift through focus. It was also observed that the process not using SRAFs with the high-k absorber had superior process window and image shift compared to the Ta-based case with SRAFs. Therefore, adoption of such high-k absorbers could potentially postpone the need for SRAFs.

Proceedings Article | 24 March 2017 Presentation + Paper

FinFET-induced anisotropy in printing of implantation shapes

Xiren Wang, Yuri Granik, Nikolay Elistratov, Christian Zuniga, Ana-Maria Armeanu, Junghwan Choi, Youngseok Woo

Proceedings Volume 10147, 1014715 (2017) https://doi.org/10.1117/12.2258346

KEYWORDS: Optical proximity correction, Critical dimension metrology, Anisotropy, Printing, Finite-difference time-domain method, Field effect transistors, Lithographic illumination, Computational lithography, Image processing, Process control, Semiconducting wafers, Reflection, 3D modeling, Silicon, Cadmium, Solids

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SPIE Journal Paper | 27 April 2016

Accurate mask model implementation in optical proximity correction model for 14-nm nodes and beyond

Nacer Zine El Abidine, Frank Sundermann, Emek Yesilada, Vincent Farys, Frederic Huguennet, Ana-Maria Armeanu, Ingo Bork, Michael Chomat, Peter Buck, Isabelle Schanen

JM3, Vol. 15, Issue 02, 021011, (April 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.2.021011

KEYWORDS: Photomasks, Calibration, Optical proximity correction, Critical dimension metrology, Electroluminescence, Wafer-level optics, Semiconducting wafers, Data modeling, 3D modeling, Scanning electron microscopy

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Proceedings Article | 23 October 2015 Paper

Accurate mask model implementation in OPC model for 14nm nodes and beyond

Nacer Zine El Abidine, Frank Sundermann, Emek Yesilada, Vincent Farys, Frederic Huguennet, Ana-Maria Armeanu, Ingo Bork, Michael Chomat, Peter Buck, Isabelle Schanen

Proceedings Volume 9635, 96350W (2015) https://doi.org/10.1117/12.2203267

KEYWORDS: Photomasks, Calibration, Critical dimension metrology, Semiconducting wafers, Optical proximity correction, Wafer-level optics, Process modeling, Data modeling, Photoresist processing, Neck

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Proceedings Article | 17 October 2014 Paper

14-nm photomask simulation sensitivity

John Sturtevant, Peter Buck, Steffen Schulze, David Fryer, Edita Tejnil, Kostas Adam, Michael Lam, Chris Clifford, Mike Oliver, Ana Armeanu, Franklin Kalk, Kent Nakagawa, Guoxiang Ning, Paul Ackmann, Fritz Gans, Christian Buergel

Proceedings Volume 9231, 92310I (2014) https://doi.org/10.1117/12.2066483

KEYWORDS: Photomasks, 3D modeling, Semiconducting wafers, Optical proximity correction, Data modeling, Calibration, Manufacturing, Photoresist materials, Metrology, Refractive index

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Proceedings Article | 1 October 2013 Paper

Full chip implant correction with wafer topography OPC modeling in 2x nm bulk technologies

J-C. Michel, J-C. Le Denmat, E. Sungauer, F. Robert, E. Yesilada, A-M. Armeanu, J. Entradas, J. Sturtevant, T. Do, Y. Granik

Proceedings Volume 8880, 88801J (2013) https://doi.org/10.1117/12.2027291

KEYWORDS: Semiconducting wafers, Optical proximity correction, Data modeling, Silicon, Calibration, 3D modeling, Photomasks, Modulation, Scanning electron microscopy, Active optics

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Proceedings Article | 12 April 2013 Paper

Wafer topography modeling for ionic implantation mask correction dedicated to 2x nm FDSOI technologies

Jean-Christophe Michel, Jean-Christophe Le Denmat, Elodie Sungauer, Frédéric Robert, Emek Yesilada, Ana-Maria Armeanu, Jorge Entradas, John Sturtevant, Thuy Do, Yuri Granik

Proceedings Volume 8683, 86830I (2013) https://doi.org/10.1117/12.2011412

KEYWORDS: Silicon, Semiconducting wafers, Oxides, Data modeling, Calibration, 3D modeling, Scanning electron microscopy, Photomasks, Process modeling, Optical lithography

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Proceedings Article | 13 March 2012 Paper

RET and DFM techniques for sub 30nm

E. Yesilada, J. Entradas, C. Gardin, J. N. Pena, A. Villaret, V. Farys, C. Beylier, F. Robert, S. Postnikov, A. M. Armeanu, C. Moyroud, F. Chaoui, F. Bernard Granger, O. Toublan

Proceedings Volume 8326, 83262H (2012) https://doi.org/10.1117/12.915825

KEYWORDS: Optical proximity correction, SRAF, Lithography, Resolution enhancement technologies, Design for manufacturing, Photomasks, Computational lithography, Inspection, Manufacturing, Optical lithography

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Showing 5 of 13 publications

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