Scientific grade Charge Coupled Device(CCD) is widely used in astronomical telescope as imaging sensor at present. A CCD camera based on CCD driving and readout ASIC is designed using CCD47-20 in this paper. The CCD driving and readout ASIC chips include CCD drive chip BCDA2(Second Edition Bias Clock Driver ASIC) and CVRA2(Second Edition CCD Video Readout ASIC). BCDA2 provides multichannel clock and bias voltage for CCD. CVRA2 processes the output signal of CCD by correlated double sampling double slope integral. The processed signals will be sampled by external ADC. Based on the BCDA2 and CVRA2, the electronics system of the camera is designed including a Connecting Board, a pre-amp board and a master control board with CCD driver and CCD readout. The test result shows it’s working well.
With the increase of human activities in space, a large number of space artifacts have been generated around the Earth which called Near Earth Objects (NEO), most of which are space debris. CMOS image sensor can achieve very high frame rate by electronical shutter and suitable for NEO observation with its fast moving. For space objects observation, key technologies of a large-format and high-rate scientific CMOS camera were studied, including low-noise readout and low-interference refrigeration technology, real-time processing algorithm, high-speed data transmission technology, system integration technology and high precision timing technology , etc. A 4K*4K pixel scientific CMOS camera is introduced in this paper with 24fps rate in full frame mode and high timing accuracy of exposure synchronization with 10ns, which has great advantages for the initial orbit positioning of the space objects. The overall size of the camera is 143mm * 160mm * 168mm. The readout noise of the camera is about 4.4e-. At present, the camera has been installed and running at Xinglong Observatory.
The Wide Field Survey Telescope (WFST) is being developed by University of Science and Technology of China and Purple Mountain Observatory. The camera of WFST is proposed to image with a mosaic Charge-coupled devices (CCD) array, which consists of 9 CCD290-99 detectors. It has requirements of decreasing the size and reducing total power dissipation for electronics system. Considering the demands of CCD290-99, two chips Application-specified Integrated Circuits (ASIC) were designed, called Second Version of Bias-Clock-Driver ASIC (BCDA2) and Second Version of CCDVideo- Readout ASIC(CVRA2) respectively. These chips have been upgraded and optimized based on the BCDA and CVRA. BCDA2 provides multi-channel clocks and biases to drive CCD290-99 and CVRA2 is used for the readout circuits of CCD signal processing. BCDA2 integrates 5 channels low noise biases with adjustable voltage and 9 channels low power dissipation clocks with adjustable driving capability. CVRA2 integrates 4 channels low noise readout circuits. Serial Peripheral Interface (SPI) was designed for configuration of BCDA2. BCDA2 and CVRA2 were designed with the Global Foundries 180 nm BCDlite technology. The area of bare chip is 3.1mm × 6mm.
The infrared astronomy is a very important branch of astronomy. Imaging observation is the basic approach to conduct infrared astronomy observation. Therefore, infrared Focus Plane Array (FPA) detector is needed for an infrared telescope. Detection toward celestial body need the detector to have high performance like extremely low dark current and low readout noise. Therefore, we designed a test equipment based on a 640 × 512 InGaAs array detector with a cryocooler which can cool the detector down to 77K. The detector is InGaAs of SITP-Hu-I type which is sensitive to 0.9us ~ 1.7um band. The test equipment is composed of a vacuum cryocooling system, a mechanical system and an electronical system. The vacuum cryocooling system can provide a low-temperature vacuum environment for the detector, and the mechanical system provides firm supporting. The electronic system provides the driver and readout of the detector.
In order to implement the driver and readout functions for several types of scientific CCD detector, meanwhile decreasing the size of electronics and reducing the total power dissipation for a large scale mosaic CCD detector system, two Application-specified Integrated Circuits (ASIC) were designed. One is for CCD driver and called BCDA (Bias Clock Driver ASIC), which is to provide multi-channel clocks and Bias voltage; the other is for CCD video processing and called CVRA (CCD Video Readout ASIC). In the BCDA chip, the bias drivers are generated by high voltage amplifiers. The clock drivers are made of a clock switch circuit and high voltage amplifier. Two 8-bit current-steering DACs are used to adjust the driver capability and high-level voltage of clocks. The CVRA chip processes the video signal of a CCD detector. The functions of CVRA chip consist of pre-amplifier, single-to-differential circuit, CDS circuit, and integrating circuit. The Global Foundry 180 nm BCDlite technology is used in this chip design. The first round of design has been finished and part of tests of two chips have been done.
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