Microprogrammable High-Speed Bit Slice Image Processor

Paul E. Thomas; Robert D. Glass

doi:10.1117/12.932525

30 July 1982 Microprogrammable High-Speed Bit Slice Image Processor

Paul E. Thomas, Robert D. Glass

Proceedings Volume 0298, Real-Time Signal Processing IV; (1982) https://doi.org/10.1117/12.932525
Event: 25th Annual Technical Symposium, 1981, San Diego, United States

Abstract

The problem of real time image processing for an Autonomous Acquisition system required the development of a special purpose high speed processor. Commercially available bit slice components were selected for the basic computational structure for speed and versatility. The processor's basic architecture is dynamically alterable into either a serial or pipelined configuration achieving higher speed than either architecture alone could provide. The high speed afforded by this structure is further enhanced by the availability of eight parallel paths allowing a maximum throughput in excess of 40 million operations per second. The algorithms which were implemented for this application include: Sobel edge, shape/connectivity, laplacian, histogram flattening and compression, a sophisticated peak detection scheme, and a "destreaking" function. Being microprogrammable, the processor will allow the implementation of additional algorithms for alter-native applications. Ensuing discussion develops the overall architecture from a functional point of view illustrating the parallelism in the architectural design which allowed the efficient implementation of this general class of algorithms.

Citation Download Citation

Paul E. Thomas and Robert D. Glass "Microprogrammable High-Speed Bit Slice Image Processor", Proc. SPIE 0298, Real-Time Signal Processing IV, (30 July 1982); https://doi.org/10.1117/12.932525

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