Bit-Serial Architecture For Real Time Motion Compensation

Raffi Dianysian; Richard L. Baker

doi:10.1117/12.969041

25 October 1988 Bit-Serial Architecture For Real Time Motion Compensation

Raffi Dianysian, Richard L. Baker

Proceedings Volume 1001, Visual Communications and Image Processing '88: Third in a Series; (1988) https://doi.org/10.1117/12.969041
Event: Visual Communications and Image Processing III, 1988, Cambridge, MA, United States

Abstract

We describe a bit-serial VLSI architecture for a real time motion estimation chip. The chip can search windows of arbitrary size with integer displacement resolution. Using 3 micron CMOS, it is projected to perform up to 6 million matches per second. This would permit real time exhaustive motion estimation of 8 x 8 blocks on 16 x 16 windows at NTSC resolution and 20 frames/sec. A short design time, without silicon assemblers or compilers, for the high speed chip is made possible by its bit-serial architecture.

Citation Download Citation

Raffi Dianysian and Richard L. Baker "Bit-Serial Architecture For Real Time Motion Compensation", Proc. SPIE 1001, Visual Communications and Image Processing '88: Third in a Series, (25 October 1988); https://doi.org/10.1117/12.969041

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