Acceleration of convolution layer in FPGA of infrared target detection algorithm

Ren-hao Cai; Li-quan Song; Peng Li; Bing-tong Zhang

doi:10.1117/12.2580137

5 November 2020 Acceleration of convolution layer in FPGA of infrared target detection algorithm

Ren-hao Cai, Li-quan Song, Peng Li, Bing-tong Zhang

Proceedings Volume 11563, AOPC 2020: Infrared Device and Infrared Technology; 115630O (2020) https://doi.org/10.1117/12.2580137
Event: Applied Optics and Photonics China (AOPC 2020), 2020, Beijing, China

Abstract

The application scene of convolution neural network is more and more extensive, which can be migrated to infrared field. A convolutional layer accelerator is designed on the FPGA to meet the needs of miniaturization and low power consumption of embedded devices. The author reduces the model about 4 times by low-bit quantization,reduces the invalid calculations through padding processing,improves computing efficiency through data flow and parallel computing, effectively reduces the computation time of the convolution layer. Ultimately, taking the SSD algorithm as an example in the FPGA, the author reduces the calculation time to about one tenth of the cpu calculation time. At the same time, the decrease degree of the macro detection result mAP50(mean average precision) caused by quantification is within 3%, and the decrease degree of detection rate and false alarm rate is within 1%.

Citation Download Citation

Ren-hao Cai, Li-quan Song, Peng Li, and Bing-tong Zhang "Acceleration of convolution layer in FPGA of infrared target detection algorithm", Proc. SPIE 11563, AOPC 2020: Infrared Device and Infrared Technology, 115630O (5 November 2020); https://doi.org/10.1117/12.2580137

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