Pattern-centric yield management approach with machine learning to detect and track defects with full chip coverage

Yu Zhang; Shirui Yu; Jiaqi Liu; Renyang Meng; Long Yin; Kai Wang; Kun Cai; Xingdi Zhang; Xinghua Song; Jiadong Ren; Abhishek Vikram; Changlian Yan; Guojie Cheng; Hui Wang; Qing Zhang; Wenkui Liao

doi:10.1117/12.2583454

22 February 2021 Pattern-centric yield management approach with machine learning to detect and track defects with full chip coverage

Yu Zhang, Shirui Yu, Jiaqi Liu, Renyang Meng, Long Yin, Kai Wang, Kun Cai, Xingdi Zhang, Xinghua Song, Jiadong Ren, Abhishek Vikram, Changlian Yan, Guojie Cheng, Hui Wang, Qing Zhang, Wenkui Liao

Author Affiliations +

Proceedings Volume 11614, Design-Process-Technology Co-optimization XV; 1161406 (2021) https://doi.org/10.1117/12.2583454
Event: SPIE Advanced Lithography, 2021, Online Only

Abstract

The importance of pattern-based defect study has grown with more complex processes in advanced semiconductor manufacturing. The pattern is the heart of the DPTCO Design Process Technology Co-Optimization approach. But the definition of pattern has been limited by the design rules that can be setup by an individual. Moreover, the huge volume of data points generated by any DRC Design Rule Check type of search forces user to sort and filter out most of them and keep only a manageable count. This effectively reduces the sample space of pattern-based learning. In this work we have employed a new approach of PCYM Pattern Centric Yield Manager where the high count of unique patterns and all its instances in full chip design is retained. It is a fundamental pillar of computational system for semiconductor fabrication where pattern-centric learning can be deployed to study any related process.

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Yu Zhang, Shirui Yu, Jiaqi Liu, Renyang Meng, Long Yin, Kai Wang, Kun Cai, Xingdi Zhang, Xinghua Song, Jiadong Ren, Abhishek Vikram, Changlian Yan, Guojie Cheng, Hui Wang, Qing Zhang, and Wenkui Liao "Pattern-centric yield management approach with machine learning to detect and track defects with full chip coverage", Proc. SPIE 11614, Design-Process-Technology Co-optimization XV, 1161406 (22 February 2021); https://doi.org/10.1117/12.2583454

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