Electrical design-for-manufacturability (DFM) checks for reducing layout-induced circuit variability of analog designs

Lynn Wang; Michael Simcoe; Vikas Mehrotra; Rais Huda; Zhao Chuan Lee; Thomas McKay; Uwe Paul Schroeder; Sriram Madhavan

doi:10.1117/12.2583839

22 February 2021 Electrical design-for-manufacturability (DFM) checks for reducing layout-induced circuit variability of analog designs

Lynn Wang, Michael Simcoe, Vikas Mehrotra, Rais Huda, Zhao Chuan Lee, Thomas McKay, Uwe Paul Schroeder, Sriram Madhavan

Author Affiliations +

Proceedings Volume 11614, Design-Process-Technology Co-optimization XV; 116140L (2021) https://doi.org/10.1117/12.2583839
Event: SPIE Advanced Lithography, 2021, Online Only

Abstract

Electrical Design-for-Manufacturability (DFM) checks are developed to quantify layout enhancements and their impact on circuit performance for analog designs. A database containing circuit topologies of analog matched devices is built. Then, connectivity checks scan the schematics for topologies from the database. If a matching topology were detected, the matched devices are mapped to layout for layout matching checks. If layout mismatches are detected, electrical DFM checks are used to quantify the imbalance in terms of parasitic resistance and capacitance. The electrical DFM checks are applied to quantify the impact due to routing, fill, and DFM fixing on three, 22nm analog design blocks. Fill insertion’s contribution to RC change is the greatest followed by routing and DFM fixing, with a maximum change of 7%, 5%, and less than 1%, respectively. Symmetry-aware layout insertions preserve the matching of electrical parameters, showing zero mismatch. All designs pass electrical DFM checks as results are within the expected design tolerances.

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Lynn Wang, Michael Simcoe, Vikas Mehrotra, Rais Huda, Zhao Chuan Lee, Thomas McKay, Uwe Paul Schroeder, and Sriram Madhavan "Electrical design-for-manufacturability (DFM) checks for reducing layout-induced circuit variability of analog designs", Proc. SPIE 11614, Design-Process-Technology Co-optimization XV, 116140L (22 February 2021); https://doi.org/10.1117/12.2583839

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