Real-Time Focal-Plane Array Image Processor

E-S. Eid; E. R. Fossum

doi:10.1117/12.969929

1 February 1990 Real-Time Focal-Plane Array Image Processor

E-S. Eid, E. R. Fossum

Proceedings Volume 1197, Automated Inspection and High-Speed Vision Architectures III; (1990) https://doi.org/10.1117/12.969929
Event: 1989 Symposium on Visual Communications, Image Processing, and Intelligent Robotics Systems, 1989, Philadelphia, PA, United States

Abstract

A focal-plane-array chip designed for real-time, general-purpose, image preprocessing is reported. A 48 X 48 pixel detector array and a 24 X 24 processing element processor array are monolithically integrated on the chip. The analog, charge-coupled device-based VLSI chip operates in the charge domain and has sensing, storing, and computing capabilities. It captures the image data and performs local neighborhood operations. The processor array is digitally programmable and uses a single-instruction, multiple-data parallel architecture. Various image preprocessing tasks such as level shifting, gain adjustment, thresholding, smoothing, sharpening, and edge detection can be implemented and A/D conversion can be performed prior to output. Frame-to-frame operations such as motion detection and tracking can be implemented as well. The chip was fabricated with a double-poly, double-metal process in a commercial CCD foundry. The prediction of the performance is based on numerical analysis and experimental results of testing a prototype charge-coupled computer. Operating at a modest clock frequency of 25 MHz, the chip is projected to achieve an internal throughput as high as 576 Mops with a 54 dB dynamic range (9-bit equivalent accuracy). The simulation of an edge detection algorithm implemented by the chip is presented. The power dissipation is estimated to be 20 mW and the total size of the 59-pad chip is 9.4 X 9.4 mm2.

Citation Download Citation

E-S. Eid and E. R. Fossum "Real-Time Focal-Plane Array Image Processor", Proc. SPIE 1197, Automated Inspection and High-Speed Vision Architectures III, (1 February 1990); https://doi.org/10.1117/12.969929

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available