Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node

R. Venkatesan; C. Guven; D. Bhawe; A. R. Greenwood; Z. Zhang; P. Gupta; P. Saksena; R. Rodriguez; N. Moumen; B. Bains; P. Sun; M. Aykol; C. Wallace; R. Bigwood; K. Fischer

doi:10.1117/12.2657778

28 April 2023 Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node

R. Venkatesan, C. Guven, D. Bhawe, A. R. Greenwood, Z. Zhang, P. Gupta, P. Saksena, R. Rodriguez, N. Moumen, B. Bains, P. Sun, M. Aykol, C. Wallace, R. Bigwood, K. Fischer

Author Affiliations +

Proceedings Volume 12495, DTCO and Computational Patterning II; 124950D (2023) https://doi.org/10.1117/12.2657778
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Abstract

This paper describes the direct print Extreme Ultra Violet (EUV) technology used for lithographic patterning of ~30-36 nm pitch metal layers of Intel 18A technology node. Direct print EUV delivers cost effective pitch scaling to enable flexible design rules and ease of use for layout designers. Careful co-optimization of the illumination source, photoresist and lithography stack is essential to resolve the tightest pitches. Optimum CDSEM metrology conditions and EUV specific requirements such as full field correction with thru slit, flare and black border compensation are critical to improve the quality of the optical proximity correction (OPC) flows. OPC algorithms were used to maximize the process window by using width sizing and pitch shifting to meet lithographic printability criteria while pushing mask manufacturability constraints to their healthy limits. The sizing of metal lines is modelled and fed to the RC extraction flows to close the fabdesign house feedback loop to improve accuracy of timing closure. A novel directional etch process enabled the direct print patterning of line tip-to-tips without requiring a second blocking mask. Multiple test masks were specifically designed to increase sensitivity of defect metrology and accelerate yield learning. Our results from multiple product vehicles demonstrate achievement of technology readiness milestones.

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Citation Download Citation

R. Venkatesan, C. Guven, D. Bhawe, A. R. Greenwood, Z. Zhang, P. Gupta, P. Saksena, R. Rodriguez, N. Moumen, B. Bains, P. Sun, M. Aykol, C. Wallace, R. Bigwood, and K. Fischer "Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node", Proc. SPIE 12495, DTCO and Computational Patterning II, 124950D (28 April 2023); https://doi.org/10.1117/12.2657778

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