Electrical analysis of a stochastically simulated 2 nm node electrical test structure

Lawrence S. Melvin III; Wolfgang Demmerle; Joachim Siebert; Phil Stopford; Sergey Zavadskiy; Renato Hentschke; Krishna Ramkumar; Sylvain Berthiaume; Yudhishthir Kandel; Wolfgang Hoppe; Ulrich Klostermann; Zachary Levinson; Hans-Jürgen Stock; Ulrich Welling

doi:10.1117/12.2658780

28 April 2023 Electrical analysis of a stochastically simulated 2 nm node electrical test structure

Lawrence S. Melvin III, Wolfgang Demmerle, Joachim Siebert, Phil Stopford, Sergey Zavadskiy, Renato Hentschke, Krishna Ramkumar, Sylvain Berthiaume, Yudhishthir Kandel, Wolfgang Hoppe, Ulrich Klostermann, Zachary Levinson, Hans-Jürgen Stock, Ulrich Welling

Author Affiliations +

Proceedings Volume 12495, DTCO and Computational Patterning II; 124950W (2023) https://doi.org/10.1117/12.2658780
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Abstract

Integrated circuit performance has been limited by transistor performance for many process nodes. However, in advanced nodes where pitches reach 10s of nanometers in size, there is an increasing probability of cases where circuit timing may be limited by the resistance and capacitance of the device rather than the transistor. This means that metal layer patterning may have implications on device performance beyond reliability, shorts, and opens. Lithography variation can be effectively predicted using stochastic simulations, including layer overlay. Simulating many patterns stochastically produces insight into the performance of the lithography process over time. Etching and metallizing the pattern set in simulation then allows the study to extend to electrical simulations. The combined lithography and electrical simulation data can then be used together to improve process or pattern performance before constructing a reticle. These data also allow the engineering teams to address resist and capacitance issues that may impact device performance prior to tapeout. This paper will investigate the metal layers of a structure designed to emulate an advanced node logic circuit that uses a CFET transistor. The structure will be corrected with OPC, and each layer will be simulated to generate a large (100) set of stochastic patterns at multiple process conditions in focus, overlay, and exposure. Each of these patterns will then be etched in a modeled process and metalized with copper. Finally, resistance and capacitance measurements will be generated from circuit simulations. The output data will then be used to update the lithography process or the pattern to improve through process performance including electrical characteristics.

Conference Presentation

Citation Download Citation

Lawrence S. Melvin III, Wolfgang Demmerle, Joachim Siebert, Phil Stopford, Sergey Zavadskiy, Renato Hentschke, Krishna Ramkumar, Sylvain Berthiaume, Yudhishthir Kandel, Wolfgang Hoppe, Ulrich Klostermann, Zachary Levinson, Hans-Jürgen Stock, and Ulrich Welling "Electrical analysis of a stochastically simulated 2 nm node electrical test structure", Proc. SPIE 12495, DTCO and Computational Patterning II, 124950W (28 April 2023); https://doi.org/10.1117/12.2658780

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available