GPU-accelerated matrix cover algorithm for multiple patterning layout decomposition

Guojin Chen; Haoyu Yang; Bei Yu

doi:10.1117/12.2657904

28 April 2023 GPU-accelerated matrix cover algorithm for multiple patterning layout decomposition

Guojin Chen, Haoyu Yang, Bei Yu

Proceedings Volume 12495, DTCO and Computational Patterning II; 124951P (2023) https://doi.org/10.1117/12.2657904
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Conference Poster

Abstract

Multiple patterning lithography (MPL) is regarded as one of the most promising ways of overcoming the resolution limitations of conventional optical lithography due to the delay of next-generation lithography technology. As the feature size continues to decrease, layout decomposition for multiple patterning lithography (MPLD) technology is becoming increasingly crucial for improving the manufacturability in advanced nodes. The decomposition process refers to assigning the layout features to different mask layers according to the design rules and density requirements. When the number of masks k ≥ 3, the MPLD problems are N P-hard and thus may suffer from runtime overhead for practical designs. However, the number of layout patterns is increasing exponentially in industrial layouts, which hinders the runtime performance of MPLD models. In this research, we substitute the CPU’s dance link data structure with parallel GPU matrix operations to accelerate the solution for exact coverbased MPLD algorithms. Experimental results demonstrate that our system is capable of full-scale, lightningfast layout decomposition, which can achieve more than 10× speed-up without quality degradation compared to state-of-the-art layout decomposition methods.

Citation Download Citation

Guojin Chen, Haoyu Yang, and Bei Yu "GPU-accelerated matrix cover algorithm for multiple patterning layout decomposition", Proc. SPIE 12495, DTCO and Computational Patterning II, 124951P (28 April 2023); https://doi.org/10.1117/12.2657904

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