Design and implementation of RISC-V-based vector operation unit for embedded processor

Zhaoyang You; Xiao Zhang; Lin Han; Rongcai Zhao

doi:10.1117/12.2680059

31 May 2023 Design and implementation of RISC-V-based vector operation unit for embedded processor

Zhaoyang You, Xiao Zhang, Lin Han, Rongcai Zhao

Proceedings Volume 12704, Eighth International Symposium on Advances in Electrical, Electronics, and Computer Engineering (ISAEECE 2023); 127040P (2023) https://doi.org/10.1117/12.2680059
Event: 8th International Symposium on Advances in Electrical, Electronics and Computer Engineering (ISAEECE 2023), 2023, Hangzhou, China

Abstract

In order to address the growing demand for vector operations in embedded systems and the urgent need to enhance vector operations in embedded systems, this paper designs a 128-bit vector operation unit based on the open source RISC-V instruction set. In order to verify the correctness of the vector operation unit, we experimentally verify the vector operation unit in the ModelSim simulation environment, and all modules meet the correctness requirements. In addition, we integrated the vector operation unit with the open-source processor Hummingbird E203 and tested it on a 16MHz FPGA development board. The results show a 1.2 times performance improvement of the demo application compared to the scalar processor.

Citation Download Citation

Zhaoyang You, Xiao Zhang, Lin Han, and Rongcai Zhao "Design and implementation of RISC-V-based vector operation unit for embedded processor", Proc. SPIE 12704, Eighth International Symposium on Advances in Electrical, Electronics, and Computer Engineering (ISAEECE 2023), 127040P (31 May 2023); https://doi.org/10.1117/12.2680059

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