Paper
16 April 1993 Deep trench process performance enhancements in an MERIE reactor
Jim Su, Graham W. Hills, Manush Birang, James A. Bondur, T. Fukamachi, S. Ohki, S. Kitamura
Author Affiliations +
Proceedings Volume 1803, Advanced Techniques for Integrated Circuit Processing II; (1993) https://doi.org/10.1117/12.142935
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States
Abstract
The development of a 16 Mb DRAM capable, deep trench etch in an applied materials P5000E, 200 mm, reactor is discussed in this paper. In order to meet the stringent device requirements extensive system modification, better process control tool development, and process optimization were necessary. The system modification activities have included: (1) a monopolar electrostatic chuck in place of the normal mechanical clamp to reduce trench profile tilt at the wafer edge, (2) an increase in cathode size, and (3) magnetic field modification. Both (2) and (3) improved the trench etch rate uniformity. For better process control, a blue laser diffraction etch rate monitor system has been demonstrated for 0.8 micrometers X 4 to approximately 7 micrometers 16 Mb trenches using two chemistries, HBr/SiF4/He-O2 and HBr/NF3/He-O2. By means of process optimization, both HBr/SiF4/He-O2 and HBr/NF3/He-O2 chemistries are able to meet the requirements for 16 Mb trench.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jim Su, Graham W. Hills, Manush Birang, James A. Bondur, T. Fukamachi, S. Ohki, and S. Kitamura "Deep trench process performance enhancements in an MERIE reactor", Proc. SPIE 1803, Advanced Techniques for Integrated Circuit Processing II, (16 April 1993); https://doi.org/10.1117/12.142935
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KEYWORDS
Etching

Semiconducting wafers

Chemistry

Magnetism

Oxides

Process control

Silicon

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