Extending resist-etch-back planarization to 0.5-um logic and ASIC circuits

Ted Regan White; W. J. Ciosek; E. J. Prinz; Charles Fredrick King; R. Blumenthal; Charles W. Stager; B. M. Somero; M. P. Woo; U. Sharma; R. W. Fiordalice; Jeff L. Klein

doi:10.1117/12.156513

15 September 1993 Extending resist-etch-back planarization to 0.5-μm logic and ASIC circuits

Ted Regan White, W. J. Ciosek, E. J. Prinz, Charles Fredrick King, R. Blumenthal, Charles W. Stager, B. M. Somero, M. P. Woo, U. Sharma, R. W. Fiordalice, Jeff L. Klein

Author Affiliations +

Proceedings Volume 2090, Multilevel Interconnection: Issues That Impact Competitiveness; (1993) https://doi.org/10.1117/12.156513
Event: Microelectronic Processing '93, 1993, Monterey, CA, United States

Abstract

This work demonstrates the extendability of a resist etch back (REB) planarization technique for use with 0.5 micrometers logic technologies. This new technique compensates for loading effects during etch back. It provides sufficient local and regional planarity for fine line patterning with i-line resists. The new REB planarization is characterized in terms of oxide thicknesses over packed and isolated lines and step heights over packed and isolated spaces. Results of the new process are compared to those of chemical-mechanical polishing in terms of metal serpentine resistances and shorts between interdigitated metal combs. The new process was integrated with collimated sputtered titanium and CVD tungsten providing high aspect ratio contacts and vias with low resistances. Sufficient photolithographic margins were obtained with REB. Together these processes meet the requirements for 0.5 micrometers logic integrated circuits with stacked vias and contacts with up to four levels of metal.

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Ted Regan White, W. J. Ciosek, E. J. Prinz, Charles Fredrick King, R. Blumenthal, Charles W. Stager, B. M. Somero, M. P. Woo, U. Sharma, R. W. Fiordalice, and Jeff L. Klein "Extending resist-etch-back planarization to 0.5-μm logic and ASIC circuits", Proc. SPIE 2090, Multilevel Interconnection: Issues That Impact Competitiveness, (15 September 1993); https://doi.org/10.1117/12.156513

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