Optimizing inline defect monitoring using correlation with electrical failures

Prashant A. Aji; Arnaud Lanier

doi:10.1117/12.275925

7 July 1997 Optimizing in-line defect monitoring using correlation with electrical failures

Prashant A. Aji, Arnaud Lanier

Proceedings Volume 3050, Metrology, Inspection, and Process Control for Microlithography XI; (1997) https://doi.org/10.1117/12.275925
Event: Microlithography '97, 1997, Santa Clara, CA, United States

Abstract

This paper describes the work done for optimization of product wafer inline monitoring using the KLA 2132 and Tencor 7700 at the SGS Thomson Rousset facility using electrical bitmapping as response. Emphasis was placed on understanding each system's capability and limitation with regards to detecting 'killer defects', as applied to different process steps. In addition speed of detection as well as signal to noise ratio were used as criteria for selecting the monitoring equipment for certain critical process steps. This experiment was carried out using a high volume product with a ROM code which made up 55 percent of the chip. The inspection was concentrated in detecting defects in this ROM area and then correlating these defects to bitmap failures.

Citation Download Citation

Prashant A. Aji and Arnaud Lanier "Optimizing in-line defect monitoring using correlation with electrical failures", Proc. SPIE 3050, Metrology, Inspection, and Process Control for Microlithography XI, (7 July 1997); https://doi.org/10.1117/12.275925

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