Thermal analysis of hot plate resist baking using a lumped capacitance model

Bo Zhou

doi:10.1117/12.350862

14 June 1999 Thermal analysis of hot plate resist baking using a lumped capacitance model

Bo Zhou

Proceedings Volume 3677, Metrology, Inspection, and Process Control for Microlithography XIII; (1999) https://doi.org/10.1117/12.350862
Event: Microlithography '99, 1999, Santa Clara, CA, United States

Abstract

Hot plate resist baking is one of the key steps in microlithographic processes. A lumped capacitance (LC) model is introduced to simulate the transient temperature of a substrate after it is thermally coupled with a hot plate. Experiments show that the first-order LC model yields reasonable accuracy except a short time period after coupling. The discrepancy between the model and experimental data is attributed to the dynamics of thermal couple that was omitted in the original model Further simulations using a second-order model that incorporates a first-order thermal couple dynamics with the LC model demonstrate excellent matching with experimental data.

Citation Download Citation

Bo Zhou "Thermal analysis of hot plate resist baking using a lumped capacitance model", Proc. SPIE 3677, Metrology, Inspection, and Process Control for Microlithography XIII, (14 June 1999); https://doi.org/10.1117/12.350862

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