Advances in second-generation ultralow-power CMOS active pixel sensor imagers for remote sensing, star tracking, optical comm, and low-cost solar array/antenna boom deployment metrology

Robert C. Stirbl; Bedabrata Pain; Thomas J. Cunningham; Bruce R. Hancock; Chao Sun; Guang Yang; Julie B. Heynssens; Christopher J. Wrigley

doi:10.1117/12.450670

12 December 2001 Advances in second-generation ultralow-power CMOS active pixel sensor imagers for remote sensing, star tracking, optical comm, and low-cost solar array/antenna boom deployment metrology

Robert C. Stirbl, Bedabrata Pain, Thomas J. Cunningham, Bruce R. Hancock, Chao Sun, Guang Yang, Julie B. Heynssens, Christopher J. Wrigley

Author Affiliations +

Proceedings Volume 4540, Sensors, Systems, and Next-Generation Satellites V; (2001) https://doi.org/10.1117/12.450670
Event: International Symposium on Remote Sensing, 2001, Toulouse, France

Abstract

JPL has implemented advances in CMOS APS visible sensors well suited for the development of ultra-low power, miniature, highly integrated image sensor systems. Applications for these low cost, modular, high performance 'camera-on-a-chip' sensors include: remote earth and planetary visible science cameras, wireless payload deployment monitors for large mirrors, solar panels, booms and antennas, and FPAs for star trackers, sun sensors and high bandwidth multi-window optical communication beacon tracker. This paper reports on the newest generation of CMOS APS dubbed the Versatile Integrated Digital Imager or VIDI APS 'camera-on-a-chip.' VIDI is an integrated, digital 'chip-camera' with a 512 X 512 format, 12-um pixels, utilizing a single 3.3 V supply, with analog or 10-bit digital output, fabricated on a standard 0.5 um CMOS process. The chip size is 10 mm X 15.5 mm. Features include a simple, all digital 'five-wire' interface, on-chip timing, control, four five-bit DACs for bias generation, and 512 column parallel ADCs, VIDI offers programmable exposure, resolution, data efficient 'smart' area-of-interest windowed high speed readout, no blooming, while continuing to operate with approximately 20 mW of power in the on-state and approximately 40 uW in the 'sleep' state and has a maximum data rate of 20 Mbits/sec.

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Robert C. Stirbl, Bedabrata Pain, Thomas J. Cunningham, Bruce R. Hancock, Chao Sun, Guang Yang, Julie B. Heynssens, and Christopher J. Wrigley "Advances in second-generation ultralow-power CMOS active pixel sensor imagers for remote sensing, star tracking, optical comm, and low-cost solar array/antenna boom deployment metrology", Proc. SPIE 4540, Sensors, Systems, and Next-Generation Satellites V, (12 December 2001); https://doi.org/10.1117/12.450670

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