Cladding layer for photonic integrated circuits

Chih-Wei Hsu; Way-Seen Wang; Hsuen-Li Chen; Tzyy-Jiann Wang; Yan Hao Huang

doi:10.1117/12.444564

16 October 2001 Cladding layer for photonic integrated circuits

Chih-Wei Hsu, Way-Seen Wang, Hsuen-Li Chen, Tzyy-Jiann Wang, Yan Hao Huang

Proceedings Volume 4603, Fiber Optics and Optoelectronics for Network Applications; (2001) https://doi.org/10.1117/12.444564
Event: International Symposium on Optoelectonics and Microelectronics, 2001, Nanjing, China

Abstract

Characterization results of cladding layer for photonic integrated circuits are present. The silicon oxide films were deposited by various methods. The mechanical stress, depending upon the methods of film deposition, had been measured. TEOS silicon oxide exhibited large mechanical stress. The stress of polymer benzocyclobutene (BCB) was also measured. Its stress is only 29 MPa. The roughness of BCB surface is 1.18 nm. The mode profiles of planar waveguide were calculated.

Citation Download Citation

Chih-Wei Hsu, Way-Seen Wang, Hsuen-Li Chen, Tzyy-Jiann Wang, and Yan Hao Huang "Cladding layer for photonic integrated circuits", Proc. SPIE 4603, Fiber Optics and Optoelectronics for Network Applications, (16 October 2001); https://doi.org/10.1117/12.444564

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