A combined noise analysis and power supply current based testing of CMOS analog integrated circuits

Ashok Srivastava; Vani K. Pulendra; Siva Yellampalli

doi:10.1117/12.609258

23 May 2005 A combined noise analysis and power supply current based testing of CMOS analog integrated circuits

Ashok Srivastava, Vani K. Pulendra, Siva Yellampalli

Proceedings Volume 5844, Noise in Devices and Circuits III; (2005) https://doi.org/10.1117/12.609258
Event: SPIE Third International Symposium on Fluctuations and Noise, 2005, Austin, Texas, United States

Abstract

A technique integrating the noise analysis based testing and the conventional power supply current testing of CMOS analog integrated circuits is presented for bridging type faults due to manufacturing defects. The circuit under test (CUT) is a CMOS amplifier designed for operation at ± 2.5 V and implemented in 1.5 μm CMOS process. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. The amplifier circuit is analyzed and simulated in SPICE for its performance with and without fault injections. The faults in the CUT are identified by observing the variation in the equivalent noise voltage at the output of CUT. In power supply current testing, the current (I_PS) through the power supply voltage, V_DD is measured under the application of an AC input stimulus. The effect of parametric variation is taken into consideration by determining the tolerance limit using the Monte-Carlo analysis. The fault is identified if the power supply current, I_PS lies outside the deviation given by Monte-Carlo analysis. Simulation results are in close agreement with the corresponding experimental values.

Citation Download Citation

Ashok Srivastava, Vani K. Pulendra, and Siva Yellampalli "A combined noise analysis and power supply current based testing of CMOS analog integrated circuits", Proc. SPIE 5844, Noise in Devices and Circuits III, (23 May 2005); https://doi.org/10.1117/12.609258

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