Design and implementation of high-speed CCD driving circuit based on CPLD

L. Zhang; Y. X. Li; X. J. Li; X. W. Xu

doi:10.1117/12.725215

11 January 2007 Design and implementation of high-speed CCD driving circuit based on CPLD

L. Zhang, Y. X. Li, X. J. Li, X. W. Xu

Proceedings Volume 6279, 27th International Congress on High-Speed Photography and Photonics; 62791M (2007) https://doi.org/10.1117/12.725215
Event: 27th International congress on High-Speed Photography and Photonics, 2006, Xi'an, China

Abstract

In CCD detecting system of dynamic target, the design of high speed CCD driving circuit is a key technique in its application. This paper, taking CCD IL-P3 produced by DALSA Company recently for example, according to the demands of CCD driving timing, introduces a designing method of high speed CCD driving circuit. A CPLD device of ALTERA Company's MAX7000S series is chosen as a hardware carrier to design the driving timing generator with adjustable exposure time. After compiled and simulated in MAX+PLUSII, the program is fitted into the CPLD device by using JTAG interface. And experimental results show that the expected CCD driving plus signals can be get.

Citation Download Citation

L. Zhang, Y. X. Li, X. J. Li, and X. W. Xu "Design and implementation of high-speed CCD driving circuit based on CPLD", Proc. SPIE 6279, 27th International Congress on High-Speed Photography and Photonics, 62791M (11 January 2007); https://doi.org/10.1117/12.725215

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