Optimizing coarse-grain reconfigurable hardware utilization through multiprocessing: an H.264/AVC decoder example

Andreas Kanstein; Sebastian López Suárez; Bjorn De Sutter

doi:10.1117/12.722077

10 May 2007 Optimizing coarse-grain reconfigurable hardware utilization through multiprocessing: an H.264/AVC decoder example

Andreas Kanstein, Sebastian López Suárez, Bjorn De Sutter

Author Affiliations +

Proceedings Volume 6590, VLSI Circuits and Systems III; 65900C (2007) https://doi.org/10.1117/12.722077
Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, Spain

Abstract

Coarse-grained reconfigurable architectures offer high execution acceleration for code which has high instruction-level parallelism (ILP), typically for large kernels in DSP applications. However for applications with a larger part of control code and many smaller kernels, as present in modern video compression algorithms, the achievable acceleration through ILP is significantly reduced. We introduce a multi-processing extension to the coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) to deal with this kind of applications, by enabling it to exploit thread-level parallelism (TLP). This extension consists of a partitioning of an ADRES array into non-overlapping parts, where every partition can execute a processing thread independently, or a processing thread can be assigned to hierarchically combined partitions which provide a larger number of resources. Because the combining of partitions can be changed dynamically, this extension provides more flexibility than a multi-core approach. This paper discusses the architecture and an exploration into how to potentially partition a given array for executing an H.264/AVC baseline decoder.

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Andreas Kanstein, Sebastian López Suárez, and Bjorn De Sutter "Optimizing coarse-grain reconfigurable hardware utilization through multiprocessing: an H.264/AVC decoder example", Proc. SPIE 6590, VLSI Circuits and Systems III, 65900C (10 May 2007); https://doi.org/10.1117/12.722077

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