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Due to the synchronization method employed by most modern digital circuits, the maximum propagation delay through
an adder unit is typically used to set the system level delay for addition operations. The actual delay of a binary addition
computation is fundamentally tied to the longest carry propagation chain created by certain input operands. Although the
probability of lengthy carry propagation chains is quite low, modern synchronous adders devote a large portion of their
silicon area and energy consumption to speeding up the propagation of carries through the adder. Therefore,
considerable die area and system power must be spent optimizing the improbable worst case delay. Using asynchronous
self-timed circuits, similar adder performance can be obtained at a fraction of the hardware cost and energy consumption.
This paper shows the inadequacy of characterizing self-timed adder performance using the assumption that typical input
operands are uniformly randomly distributed, and presents a new self-timed adder characterization benchmark based on
the SpecINT 2000 benchmark suite. The SpecINT 2000 benchmark was selected since there is no published carry
propagation chain distribution for this modern benchmark suite and the benchmark is well suited for measuring carry
propagation chains due to its code size and the fact that it is a non-synthetic benchmark. All totaled, over 4.7 billion
addition/subtraction operations resulting from address and data calculations were tabulated to create the SpecINT 2000
Carry Propagation Distribution. This new carry propagation distribution sheds light on the accuracy of existing
distributions based on the Dhrystone integer benchmark and demonstrates how measuring self-timed adder performance
with a uniformly random input distribution can overestimate self-timed adder performance by over 50 percent.
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