Predicting yield using model based OPC verification: calibrated with electrical test data

James A. Bruce; Tso-Hui Ting

doi:10.1117/12.773591

4 March 2008 Predicting yield using model based OPC verification: calibrated with electrical test data

James A. Bruce, Tso-Hui Ting

Proceedings Volume 6925, Design for Manufacturability through Design-Process Integration II; 69250S (2008) https://doi.org/10.1117/12.773591
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States

Abstract

Electrically testable structures (such as serpentines for testing opens and serpentine/combs for testing shorts) with varying post-OPC dimensions have been incorporated into test reticles, which were then used to process wafers through electrical test. Process window OPC verification was run on the same structures, thus allowing correlation of electrical yield to OPC-verification results. By combining OPC verification results with probability of occurrence for the various process conditions used in OPC verification, a predicted yield can be calculated. Comparisons of electrical yield to predicted yield are used to demonstrate a methodology for verifying (or setting) failure limits. Although, in general, the correlation between electrical and predicted yield is reasonable, various issues have been identified which impact this correlation, and make the task of accurately predicting yield difficult. These issues are discussed in detail in this paper.

Citation Download Citation

James A. Bruce and Tso-Hui Ting "Predicting yield using model based OPC verification: calibrated with electrical test data", Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250S (4 March 2008); https://doi.org/10.1117/12.773591

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