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Design rules for logic device have been defined by technology requirement like shrink rate of chip area or process
capability of lithography and other processes. However, those rules are usually only for minimum pitches or minimum
sizes of simple layout, such as line and space patterns with enough long common run length, no intermediate corners, no
jogs and no asymmetry patterns. On the other hand, actual chip layout includes many variations of pattern which often
cause trouble in wafer manufacturing process due to their less process capability, would be found far later when the
design rules are fixed. To solve this issue, additional design rules for two-dimensional patterns, such as line-end to lineend
space, are necessary and have been applied into recent design rules. It is hard to check such many variations of
pattern by the experiment with actual wafer, so checking by lithography simulation in advance is very effective way to
estimate and fix design rules for these two dimensional patterns.
To estimate rules with accuracy, and to minimize numbers in each rule for chip area reduction, OPC and RET must be
included in the estimation, particularly for recent low-k1 lithography. However, OPC and RET are also immature in the
early development term, when design rules are necessary for designers to prepare a test mask to develop the device,
process and some parts of circuit. In other words, OPC, RET and design rules have been modified in parallel, sometime
new RET would be required to achieve a rule, sometime the design rules would be required to relax their numbers, and
sometime new design rules would be required to avoid less process capability.
In this paper, we propose the parallel development procedure for OPC, RET and design rules through the actual
development of 45nm node logic device, focused on metal layer which has many pattern variations, and show how to
build the competitive design rules by applying the latest OPC and RET technologies.
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