Implementation of weighted summation type fractional Fourier transform on FPGA

Qiming Zou; Longlong Li; Qian Huang; Fei Wang

doi:10.1117/12.2197111

6 July 2015 Implementation of weighted summation type fractional Fourier transform on FPGA

Qiming Zou, Longlong Li, Qian Huang, Fei Wang

Proceedings Volume 9631, Seventh International Conference on Digital Image Processing (ICDIP 2015); 963125 (2015) https://doi.org/10.1117/12.2197111
Event: Seventh International Conference on Digital Image Processing (ICDIP15), 2015, Los Angeles, United States

Abstract

Recently Fractional Fourier transform (FrFT) has got a variety of applications in digital signal and image processing. This paper presents a novel hardware architecture for real-time computation of Discrete Fractional Fourier Transform (DFrFT), which can easily be extended to other fractional transforms. The proposed architecture has been verified on Xilinx FPGA(XC6VLX240T), which can run at a frequency up to 291MHz while with high accuracy.

Citation Download Citation

Qiming Zou, Longlong Li, Qian Huang, and Fei Wang "Implementation of weighted summation type fractional Fourier transform on FPGA", Proc. SPIE 9631, Seventh International Conference on Digital Image Processing (ICDIP 2015), 963125 (6 July 2015); https://doi.org/10.1117/12.2197111

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available