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The basic principle of Moore's law invokes scaling transistor density at favorable cost. Scaling transistor density implies shrinking feature size more than ever before. Over time, patterning variability control has emerged to become the most critical challenge to continued shrinking of feature sizes. Breaking this down further, continued scaling requires patterning to meet three critical challenges: the ability to print at tight pitch, the ability to place patterns accurately with respect to each other and the ability to deal with pattern variations (example: metal fill, reliability, etc). The advent of EUV (0.33NA now and High NA in near future) has certainly alleviated or simplified some challenges, however metal layers ≤ 22nm pitch would likely require multiple passes of EUV. Cost of multiple high-dose EUV passes could become a challenge by itself, not to mention that high variability of tight pitch features remains a key challenge for EUV in general. In 2022 we (Intel) demonstrated a novel complementary patterning method combining spacer-based double patterning (SADP) in conjunction with low-dose EUV and Directed Self-Assembly (DSA) to create low-defectivity, low roughness ≤ 21nm pitch metal gratings with self-aligned plugs. Here we go further and show electrical validation and yield results of this novel approach as well as new innovations in process and chemistry that will enable next generation of DSA technology in pursuit of continuing Moore's law.
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