Design of an optimization scheme for compressed circuits in hardware implementation of large number multiplication

Cheng Su; Hong Xia; Pan Zhao; Wenyuan Lei

doi:10.1117/12.3011132

2 November 2023 Design of an optimization scheme for compressed circuits in hardware implementation of large number multiplication

Cheng Su, Hong Xia, Pan Zhao, Wenyuan Lei

Author Affiliations +

Proceedings Volume 12919, International Conference on Electronic Materials and Information Engineering (EMIE 2023); 129190K (2023) https://doi.org/10.1117/12.3011132
Event: 3rd International Conference on Electronic Materials and Information Engineering (EMIE 2023), 2023, Guangzhou,, China

Abstract

The frequent use of 1024-bit large number multiplication in encryption algorithms like SM9 often involves parallel execution of multiple small-bit Booth multipliers. However, this design approach leads to significant area consumption in the compression circuit and intermediate registers. In this paper, we propose a novel reconfigurable and reusable compressed circuit design that reduces the area of the compression circuit without compromising speed, thus minimizing the overall area of the large number multiplication circuit. The proposed design is simulated using Design Compiler in the SMIC0.18 technology library under the SSG process corner. The results demonstrate a 21% reduction in circuit area and a 2% decrease in power consumption.

(2023) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Cheng Su, Hong Xia, Pan Zhao, and Wenyuan Lei "Design of an optimization scheme for compressed circuits in hardware implementation of large number multiplication", Proc. SPIE 12919, International Conference on Electronic Materials and Information Engineering (EMIE 2023), 129190K (2 November 2023); https://doi.org/10.1117/12.3011132

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