There has been many low-swing on-chip interconnect signaling techniques introduced to tackle the problem of inverse-scaling
effect of on-chip wires. This paper proposes a comparison framework using SPICE-based simulations on the
90nm technology node, which is needed to assess the effectiveness of a certain interconnect technique over the others
with a high degree of objectiveness and accuracy. Two low-swing techniques are included in the comparison, i.e.
conventional level converter (CLC) and current-mode signaling (CM). These techniques were chosen to represent
different driver and receiver topologies, where CLC uses lower driver supply voltage, while CM has a low impedance
termination at receiver end. In addition, an optimized full-swing repeater-based technique is included as a baseline for
comparison. The main contribution of this paper is the identification of circuit and wire design parameters that affects
performances the most, leading to a design guideline with reduced set of design variables for delay or energy
optimization of each technique. A simplified repeater performance estimation technique considering ramp input signals
is also proposed. Furthermore, trade-off between energy and delay using the optimization processes has been explored,
resulting in a more objective comparison of different interconnect techniques in the power-delay space. Results show
that optimized CLC (reduced voltage supply) repeaters can perform better in both terms of delay and power in its design
performance range.
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