The aim of the work is to present a theoretical model of tunnel field effect transistor and to investigate the influence of the TFET’s construction parameters on the current-voltage characteristics. The solution to the problem of electrostatics in the structure is based on the numerical solution of two-dimensional Poisson equation and the electron and hole continuity equations. The tunneling process has been taken into account by a non-local interband generation model. Output and transfer characteristics of the double gate TFET were generated.
In this work we present the investigations aimed at the optimization of the technology of Reactive Ion Etching in sulfur hexafluoride (SF6) plasma of silicon, which is necessary during fabrication of TFET according to the original concept of the device designed at Institute of Microelectronics and Optoelectronics (IMiO) of Warsaw University of Technology (WUT) laboratory. We have performed a two-stage optimization of RIE process’ parameters in order to obtain a controllable process characterized by good selectivity and anisotropy. Presented in this study findings have shown that the SF6 flow most significantly influence onto the RIE process’ results. Selected and optimized processing step will be used in the course of the fabrication of TFET devices, in future.
Interface traps density (Nit) and gate insulator thickness (tox) impact on MIS tunnel structure electrical characteristics is discussed in respect to bias voltage range corresponding to inversion in the semiconductor substrate region. Effect of Nit and tox on equilibrium and non-equilibrium operation regime of the device is presented. Different models of the small-signal response of interface traps are proposed and discussed in respect to several phenomena related to the traps charging and discharging processes. Presented analysis was performed for the MIS structures with the gate dielectric made of silicon dioxide (SiO2) and hafnium oxide (HfOx). The obtained results proved that the surface density of interface traps (Nit) and the insulator thickness (tox) have correlated impact on the transition between equilibrium and non-equilibrium operation of the MIS tunnel structures.
We present the study of impact of the nanocrystal position and oxide layers thicknesses of the metal-insulatorsemiconductor structure with nanocrystals embedded in the insulator layer on the time-dependent current-voltage and capacitance-voltage characteristics. The theoretical considerations are based on the developed numerical model of a double-barrier MOS structure. The dominant current path in the structure is analysed in respect to the nanocrystals charging/discharging processes.
An influence of the potential in the quantum well in the DB MOS structure on its current-voltage characteristics is
considered under the assumption of a sequential tunneling through the double barrier system due to the effective
recombination in the well.
Analysis of the temperature effect on electrical characteristics of double barrier metal-oxide-semiconductor structure is
presented in the work. Results of the simulation of electrical characteristics obtained with the original theoretical model
are compared with the measurements of the fabricated DB MOS structure.
A description of the tunnel current in the metal-insulator-metal structure including Coulomb blockade is considered,
which reduces to a commonly known “orthodox model” for sufficiently low temperatures. The current-voltage
characteristics are calculated for various variants of the description and various parameters of the MIM structure.
Drain current and transconductance of a symmetrical, undoped double-gate MOSFET is modeled for the first time with
mobility depending on both the applied voltage and position in the channel leading to analytical formulae. The obtained
models are compared with simplified formulae assuming position-independent effective mobility. Good agreement is
obtained in the case of one of the selected mobility models.
The detailed investigations of degradation processes, their characterization and understanding of mechanisms responsible for degradation is of great technological interest, both from the fabrication point of view, and as a long-term reliability concern. Some of the effects usually need investigation in the completed MOS transistor structure (hot carrier degradation, threshold voltage, and channel mobility deterioration), but others should be studied with the special test structures so that effects can be investigated independently (electromigration, radiation effects, oxide wear-out). The paper presents a review of problems related to reliability of VLSI ICs, degradation processes, and their characterization.
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