The knowledge of carrier concentration of doped or non-intentionally doped layer structures grown by Molecular Beam Epitaxy (MBE) is crucial to fabricate and manage design of new advanced photodetectors called "barrier structures". This communication reports on capacitance-voltage (C-V) study on MOS structure. Simulation to define specific MOS design, allowing doping layer concentration extraction by measurements, is performed. MOS structures based on InAs/GaSb Longwave infrared (LWIR) superlattice have been fabricated and characterized. Results obtained were analyzed and compared with simulations.
KEYWORDS: Oxides, Transistors, Data modeling, Interfaces, Field effect transistors, Instrument modeling, Dielectrics, Signal to noise ratio, Electrons, Analog electronics
An analytical model for 1/f gate noise is developed and applied to the simulation and the characterization of ultra-thin
MOSFETs. The proposed model is based on oxide trapping mechanisms and uses the concept of equivalent flat band
voltage fluctuations. The developed model reproduces experimental behaviors. The power spectral density of flat band
voltage fluctuation extracted from gate current low frequency noise is compared to one extracted from drain low
frequency noise. Moreover, we have performed 1/f gate current noise for various drain voltage, and we show that there is
no impact of the drain current noise on the gate current noise. We also investigate RTS noise observed on the gate
leakage current. Finally, we present the characterization of the gate to drain overlap leakage current and its influence on
gate current noise level.
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