I have been involved in the research of single photon timing applications since 2013. My main research interests concern the design and development of all the integrated electronics required to extract the timing information with extremely high performance from Single Photon Avalanche Diodes and to achieve high speed with these sensors in both counting and timing applications. Being a front end and processing IC designer has given to me the opportunity of gaining a broad knowledge in the field, from device to overall system issues.
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During the last years, much effort has been made towards the parallelization of many acquisition and conversion chains. In particular, the exploitation of Single-Photon Avalanche Diodes in standard CMOS technology has paved the way to the integration of thousands of independent channels on the same chip.
Unfortunately, the presence of a large number of detectors can give rise to a huge rate of events, which can easily lead to the saturation of the transfer rate toward the elaboration unit. As a result, a smart readout approach is needed to guarantee an efficient exploitation of the limited transfer bandwidth.
We recently introduced a novel readout architecture, aimed at maximizing the counting efficiency of the system in typical TCSPC measurements. It features a limited number of high-performance converters, which are shared with a much larger array, while a smart routing logic provides a dynamic multiplexing between the two parts.
Here we propose a novel routing algorithm, which exploits standard digital gates distributed among a large 32x32 array to ensure a dynamic connection between detectors and external time-measurement circuits.
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