Redundant representations are used to increase the performance of
arithmetic units. If redundancy is eliminated, the bits needed to
represent a number may increase or decrease depending on the type of
redundancy used. In such a redundant representation, finding the exact
location and correct decision for rounding without eliminating the
redundancy or loosing its performance gains is difficult. This paper
discusses the different issues related to rounding in redundant systems. It also presents a solution that was used to maintain the gains of redundancy in a floating point unit while correctly implementing the IEEE rounding modes.
KEYWORDS: Multiplexers, Logic, Signal processing, Transistors, Logic devices, Digital signal processing, Systems modeling, Visualization, Computer simulations, Device simulation
A parametric time delay model to compare floating point unit implementations is proposed. This model is used to compare a previously proposed floating point adder using a redundant number representation with other high-performance implementations. The operand width, the fan-in of the logic gates and the radix of the redundant format are used as parameters to the model. The comparison is done over a range of operand widths, fan-in and radices to show the merits of each implementation.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.